Fast, Accurate Assembly-Level Physical Verification of 3DIC Packages

Abstract

Advanced packaging techniques are critical to ensuring product performance, function, and cost in the semiconductor industry. Three-dimensional integrated circuits (3DICs) offer the ultimate flexibility in product design. However, they are not without their challenges, bringing packaging technologies to the forefront for innovation. 3DICs contain multiple stacked die that achieve the required connectivity through traces on an interposer, or with special vias or bumps. Independently verifying the physical and connectivity accuracy of these discrete dies and substrates per their process rules does not ensure that the overall 2.5D/3D package assembly is correct, or will perform as expected. The Calibre 3DSTACK electronic design automation (EDA) tool provides fast, accurate, assembly-level verification of die-die or die-interposer interfaces in 3DIC designs. It operates on the interface geometries between chip designs from multiple process nodes to perform both design rule checking (DRC) alignment verification and layout vs. schematic (LVS) connectivity checking of the complete multi-die 2.5D or 3DIC system. Design engineers can also use the Calibre 3DSTACK tool to prepare the data required for coupling capacitance extraction, if required. In this paper, we explain the differences between traditional 3DIC physical verification techniques and Calibre 3DSTACK 3DIC assembly verification, and demonstrate how Calibre 3DSTACK functionality can be used to resolve many of the challenges of 3DIC physical verification while ensuring the accuracy and performance of the complete 3DIC design.