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2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software最新文献

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Power-Supply Noise Attributed Timing Jitter in Nonoverlapping Clock Generation Circuits 非重叠时钟产生电路中电源噪声引起的时序抖动
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321029
A. Strak
{"title":"Power-Supply Noise Attributed Timing Jitter in Nonoverlapping Clock Generation Circuits","authors":"A. Strak","doi":"10.1109/DCAS.2006.321029","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321029","url":null,"abstract":"This paper describes an analysis of timing jitter induced by power-supply noise in nonoverlapping clock generation circuits typically used in switched-capacitor sigma-delta modulators. Substrate noise effects are also included but not treated as a separate phenomenon since the MOSFET bulk contacts are connected to the power-supply or ground. Two different nonoverlapping clock generation circuits have been compared and treated independently: the NOR based and the NAND based architectures. Furthermore, all possible connection topologies of the circuit blocks in the clock generation circuits are investigated. Monte Carlo simulations have been performed in Spectre at BSIM3v3 transistor model level using parameters from a 0.18mum process to show which of the topologies is most suitable as clock generator for wideband applications. In terms of timing jitter sensitivity to power-supply noise, the NOR based architecture is slightly more robust and suitable for providing a timing reference to a sampling circuit","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114660463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimal Gate Size Selection for Standard Cells in a Library 库中标准单元栅极尺寸的最优选择
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321030
V. Singhal, G. Girishankar
{"title":"Optimal Gate Size Selection for Standard Cells in a Library","authors":"V. Singhal, G. Girishankar","doi":"10.1109/DCAS.2006.321030","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321030","url":null,"abstract":"Standard cell libraries provide designers with a fixed set of well characterized logic blocks. As designs are pushed for high performance, low area, and low power, it is essential to have a, good standard cell library that can help achieve these goals. As gate sizing is crucial to timing, the number of gate sizes (drive strengths) available for each of the primitives is an important factor to be considered. While an infinite granularity of gate sizes is preferable to get the best entitlement, it is often impractical due to the huge cost associated with developing and maintaining libraries. It is therefore essential to find ways to achieve the best performance, power and area, with a, reasonable library size. In this paper we focus on the problem of finding out the optimal ratio of gate sizes to be selected. 65nm libraries were used for validating the claims on a real design and the results are presented in this paper","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129136242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability 利用布尔可满足性的可逆逻辑的精确Toffoli网络综合
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321031
D. Grobe, Xiaobo Chen, R. Drechsler
{"title":"Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability","authors":"D. Grobe, Xiaobo Chen, R. Drechsler","doi":"10.1109/DCAS.2006.321031","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321031","url":null,"abstract":"Compact synthesis result for reversible logic is of major interest in low-power design and quantum computing. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean satisfiability (SAT) instances. Such an instance is satisfiable iff there exists a network representation with d gates. Thus we can guarantee minimality. For a set of benchmarks experimental results are given","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123084577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Fixed-Point Implementation for QR Decomposition QR分解的定点实现
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321037
C. Singh, S.H. Prasad, P. Balsara
{"title":"A Fixed-Point Implementation for QR Decomposition","authors":"C. Singh, S.H. Prasad, P. Balsara","doi":"10.1109/DCAS.2006.321037","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321037","url":null,"abstract":"Matrix triangularization and orthogonalization are prerequisites to solving least square problems and find applications in a wide variety of communication systems and signal processing applications such as MIMO systems and matrix inversion. QR decomposition using modified Gram-Schmidt (MGS) orthogonalization is one of the numerically stable techniques used in this regard. This paper presents a fixed point implementation of QR decomposition based on MGS algorithm using a novel LUT based approach. The proposed architecture is based on log-domain arithmetic operations. The error performance of various fixed-point arithmetic operations has been discussed and optimum LUT sizes are presented based on simulation results for various fractional-precisions. The proposed architecture also paves way for an efficient parallel VLSI implementation of QR decomposition using MGS","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116806019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Cellular handset integration 手机集成
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321025
B. Krenik
{"title":"Cellular handset integration","authors":"B. Krenik","doi":"10.1109/DCAS.2006.321025","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321025","url":null,"abstract":"The article examines cellular wireless evolution from 1G (analog cellular) up to the present day, 4G (wideband network). The following conclusions are made: approximately 1 billion phones/year to be produced; cost challenge in low end market; there are higher costs, areas and power in the high end; lots of air interfaces are available; Moore's Law meets logic and memory challenge; single-chip integration offers compelling benefit for analog/RF; and new air interfaces are coming soon.","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114586029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design Methodology of On-Chip Power Distribution Network 片上配电网的设计方法
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321038
H. Tohya, N. Toya
{"title":"Design Methodology of On-Chip Power Distribution Network","authors":"H. Tohya, N. Toya","doi":"10.1109/DCAS.2006.321038","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321038","url":null,"abstract":"The effect of the capacitors in the power distribution network (PDN) was reviewed based on electromagnetic theory. It was clarified that the capacitors used in the PDN are not suitable for high-frequency decoupling or for lowering the impedance. Based on this result, a novel design methodology of an on-chip PDN is proposed in this paper. The low-impedance lossy line (LILL) technology is used as the PDN instead of capacitors and other components. This methodology improves both the performance of the SoC and also the signal transmission rate markedly because the LILL in the PDN shortens the rise time of the signal. An analysis of the effect of the novel design methodology, SPICE simulation result, and an example of an on-chip LILL structure for the SoC are presented in this paper","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114984866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Ring Oscillator Performance and Parasitic Extraction Simulation in Finfet Technology Finfet技术中环形振荡器性能及寄生提取仿真
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321049
M. Kulkarni, A. Marshall, C. Rinn Cleavelin, W. Xiong, C. Pacha, K. von Armin, T. Schulz, K. Schruefer, P. Patruno
{"title":"Ring Oscillator Performance and Parasitic Extraction Simulation in Finfet Technology","authors":"M. Kulkarni, A. Marshall, C. Rinn Cleavelin, W. Xiong, C. Pacha, K. von Armin, T. Schulz, K. Schruefer, P. Patruno","doi":"10.1109/DCAS.2006.321049","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321049","url":null,"abstract":"Correlation of a full parasitic extracted simulation using StarRC and SPICE to silicon is demonstrated for fully depleted (FD) FinFET silicon-on-insulator ring oscillators. The results indicate similar accuracy can be expected as obtained from bulk simulations. This is important in integrated circuit development, as the accurate simulation of circuit performance is imperative to IC development","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130163299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Noise Analysis of Time-to-Digital Converter in All-Digital PLLs 全数字锁相环时数转换器的噪声分析
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321040
S. Vamvakos, R. Bogdan Staszewski, M. Sheba, K. Waheed
{"title":"Noise Analysis of Time-to-Digital Converter in All-Digital PLLs","authors":"S. Vamvakos, R. Bogdan Staszewski, M. Sheba, K. Waheed","doi":"10.1109/DCAS.2006.321040","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321040","url":null,"abstract":"In an all-digital PLL architecture the conventional phase-frequency detector is replaced in part by a time-to-digital converter. This paper presents an exact analysis of the mechanism by which reference clock jitter and/or supply/substrate noise are converted into TDC noise that is injected into the ADPLL loop. The cases of white and sinusoidal noise are considered and the analytical results are compared with simulations","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115482852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Fractional-N Frequency Synthesizer- A Novel Approach 分数n频率合成器——一种新方法
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321052
Xiao Pu, A. Thomsen
{"title":"Fractional-N Frequency Synthesizer- A Novel Approach","authors":"Xiao Pu, A. Thomsen","doi":"10.1109/DCAS.2006.321052","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321052","url":null,"abstract":"A charge pump free, divider less fractional-N frequency synthesizer is proposed. The goal of this study is to design a wideband PLL by utilizing front-end analog signal processing to extract phase information from sinusoidal references. Compared to conventional charge pump PLLs, the phase information is updated at a faster rate, thus a wider bandwidth (BW) can be achieved. The synthesizer is intended for wireless communication applications. Matlab simulations are used to illustrate how the new PLL architecture works, and where the design challenges reside","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124139623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Built-in Tester for Modulation Noise in a Wireless Transmitter 无线发射机调制噪声内置测试仪
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321033
O. Eliezer, O. Friedman, R. Staszewski
{"title":"A Built-in Tester for Modulation Noise in a Wireless Transmitter","authors":"O. Eliezer, O. Friedman, R. Staszewski","doi":"10.1109/DCAS.2006.321033","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321033","url":null,"abstract":"A fully digital implementation for an RF built-in self-test (RF BIST), incorporated within a digital RF processor (DRPtrade)-based system-on-chip (SoC), is presented. The proposed mechanism serves as an on-chip built-in modulation-noise estimation-module (BIMNEM) for the testing of the 2.4 GHz local oscillator of a Bluetooth transceiver offered by Texas Instruments. This SoC, realized in a standard 130 nm digital CMOS process, is being tested in mass production using a digital very-low-cost-tester (VLCT) that leverages on the internal test capabilities of the SoC, thereby minimizing test costs. Experimental results are shown and the extension of this approach for implementation in the later generations of DRP based SoCs is briefly discussed","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126498436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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