片上配电网的设计方法

2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI:10.1109/DCAS.2006.321038

H. Tohya, N. Toya

{"title":"片上配电网的设计方法","authors":"H. Tohya, N. Toya","doi":"10.1109/DCAS.2006.321038","DOIUrl":null,"url":null,"abstract":"The effect of the capacitors in the power distribution network (PDN) was reviewed based on electromagnetic theory. It was clarified that the capacitors used in the PDN are not suitable for high-frequency decoupling or for lowering the impedance. Based on this result, a novel design methodology of an on-chip PDN is proposed in this paper. The low-impedance lossy line (LILL) technology is used as the PDN instead of capacitors and other components. This methodology improves both the performance of the SoC and also the signal transmission rate markedly because the LILL in the PDN shortens the rise time of the signal. An analysis of the effect of the novel design methodology, SPICE simulation result, and an example of an on-chip LILL structure for the SoC are presented in this paper","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design Methodology of On-Chip Power Distribution Network\",\"authors\":\"H. Tohya, N. Toya\",\"doi\":\"10.1109/DCAS.2006.321038\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The effect of the capacitors in the power distribution network (PDN) was reviewed based on electromagnetic theory. It was clarified that the capacitors used in the PDN are not suitable for high-frequency decoupling or for lowering the impedance. Based on this result, a novel design methodology of an on-chip PDN is proposed in this paper. The low-impedance lossy line (LILL) technology is used as the PDN instead of capacitors and other components. This methodology improves both the performance of the SoC and also the signal transmission rate markedly because the LILL in the PDN shortens the rise time of the signal. An analysis of the effect of the novel design methodology, SPICE simulation result, and an example of an on-chip LILL structure for the SoC are presented in this paper\",\"PeriodicalId\":244429,\"journal\":{\"name\":\"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCAS.2006.321038\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2006.321038","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

从电磁理论的角度综述了电容器在配电网中的作用。澄清了PDN中使用的电容器不适合高频去耦或降低阻抗。基于这一结果，本文提出了一种新的片上PDN设计方法。采用低阻抗损耗线(LILL)技术代替电容器和其他元件作为PDN。这种方法既提高了SoC的性能，也显著提高了信号的传输速率，因为PDN中的LILL缩短了信号的上升时间。文中分析了新设计方法的效果，给出了SPICE仿真结果，并给出了片上lll结构的一个例子

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design Methodology of On-Chip Power Distribution Network

The effect of the capacitors in the power distribution network (PDN) was reviewed based on electromagnetic theory. It was clarified that the capacitors used in the PDN are not suitable for high-frequency decoupling or for lowering the impedance. Based on this result, a novel design methodology of an on-chip PDN is proposed in this paper. The low-impedance lossy line (LILL) technology is used as the PDN instead of capacitors and other components. This methodology improves both the performance of the SoC and also the signal transmission rate markedly because the LILL in the PDN shortens the rise time of the signal. An analysis of the effect of the novel design methodology, SPICE simulation result, and an example of an on-chip LILL structure for the SoC are presented in this paper

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software

自引率

0.00%

发文量