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2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software最新文献

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Random Sampling for Analog-to-Information Conversion of Wideband Signals 宽带信号模拟-信息转换的随机采样
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-12-01 DOI: 10.1109/DCAS.2006.321048
J. Laska, S. Kirolos, Y. Massoud, Richard Baraniuk, A. Gilbert, M. Iwen, M. Strauss
{"title":"Random Sampling for Analog-to-Information Conversion of Wideband Signals","authors":"J. Laska, S. Kirolos, Y. Massoud, Richard Baraniuk, A. Gilbert, M. Iwen, M. Strauss","doi":"10.1109/DCAS.2006.321048","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321048","url":null,"abstract":"We develop a framework for analog-to-information conversion that enables sub-Nyquist acquisition and processing of wideband signals that are sparse in a local Fourier representation. The first component of the framework is a random sampling system that can be implemented in practical hardware. The second is an efficient information recovery algorithm to compute the spectrogram of the signal, which we dub the sparsogram. A simulated acquisition of a frequency hopping signal operates at 33times sub-Nyquist average sampling rate with little degradation in signal quality","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121248049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 257
An Approach to Interference Detection for Ultra Wideband Radio Systems 一种超宽带无线电系统干扰检测方法
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321041
Tien-Ling Hsieh, P. Kinget, R. Gharpurey
{"title":"An Approach to Interference Detection for Ultra Wideband Radio Systems","authors":"Tien-Ling Hsieh, P. Kinget, R. Gharpurey","doi":"10.1109/DCAS.2006.321041","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321041","url":null,"abstract":"This paper presents an interference detection technique based on analog spectral decomposition for a multi-band ultra wideband (UWB) radio system. The architecture utilizes a cascade of image-rejecting single-sideband mixers with fixed LO frequencies. The proposed technique can rapidly detect portions of the spectrum with the largest interference levels and provide information to avoid transmission and reception in those bands. This information can be used to relax the dynamic range of the receiver and reduce the potential for interference-related signal degradation","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"20 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126944755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Efficient Procedures for Analyzing Large-Scale RF Circuits 分析大规模射频电路的有效程序
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321034
J. Dobes
{"title":"Efficient Procedures for Analyzing Large-Scale RF Circuits","authors":"J. Dobes","doi":"10.1109/DCAS.2006.321034","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321034","url":null,"abstract":"The majority of CAD tools have limited modes of the sensitivity analysis: PSPICE only contains a static mode and SPECTRE includes frequency domain and static modes. However, many RF systems use symmetrical structures for enhancing the properties of the circuits. For such systems, the static sensitivities are zero in principle and therefore the time domain sensitivity analysis must be used. In the paper, a new recurrent formula for the time domain sensitivity analysis is derived, which uses by-products of an implicit integration algorithm. Moreover, for a very fast estimation of mixed products, an efficient procedure is described, which is also not implemented in PSPICE. Both methods are demonstrated by analyses of a four-quadrant RF multiplier","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131768136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliable Interconnect Grid for Ultra Deep Submicron 可靠的超深亚微米互连网格
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321045
A. Namazi, M. Nourani, M. Saquib
{"title":"Reliable Interconnect Grid for Ultra Deep Submicron","authors":"A. Namazi, M. Nourani, M. Saquib","doi":"10.1109/DCAS.2006.321045","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321045","url":null,"abstract":"Reliability of the interconnects has become a challenge in deep submicron technology. In this paper, we propose grid communication strategy that establishes highly reliable interconnects with no length limitation. We show that using direct sequence spread spectrum and inexpensive transceivers we can transfer data with extremely low error rates. Such a highly reliable communication network is vital for future ultra deep submicron and nano systems. Experimental results are also reported to verify the concept, clarify the design procedure and measure the communication grid metrics","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"09 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120822456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Phase Noise Reduction in High Speed Frequency Divider 高速分频器的相位降噪
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321039
Rahul Prakash, Siraj Akhtar, Poras T. Balsaral
{"title":"Phase Noise Reduction in High Speed Frequency Divider","authors":"Rahul Prakash, Siraj Akhtar, Poras T. Balsaral","doi":"10.1109/DCAS.2006.321039","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321039","url":null,"abstract":"Maximum operating frequency, phase noise characteristics close to output carrier frequency and power consumption during operation are major parameters of a frequency divider. Since these parameters are interrelated, design optimization involves tradeoffs among them. A new differential D-latch based topology for a low phase noise frequency divider for cellular transceivers is presented. An optimization process for the design of frequency divider is given and various phenomena that dominate phase noise and high frequency behavior of the frequency dividers are discussed. The proposed divider designed using 65 nm CMOS has a maximum input frequency of 11.8 GHz with phase noise level of 153.3 dBc/Hz at an offset of 20 MHz. It consumes 11 mA average current while operating at a nominal frequency of 8 GHz","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132386489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Spur-Free Fractional-N PLL Utilizing Precision Frequency and Phase Selection 利用精确频率和相位选择的无杂散分数n锁相环
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321053
E. Bilhan, F. Ying, J. Meiners, Liming Xiu
{"title":"Spur-Free Fractional-N PLL Utilizing Precision Frequency and Phase Selection","authors":"E. Bilhan, F. Ying, J. Meiners, Liming Xiu","doi":"10.1109/DCAS.2006.321053","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321053","url":null,"abstract":"An architecture for fractional-N frequency synthesis is presented. The proposed topology does not use the traditional method of obtaining the fractional division via an average of N and N+1 divided clock cycles. Instead, it uses the equally spaced phases provided from a ring oscillator that works as VCO to generate the fractional frequency. Therefore, the proposed architecture does not generate any spurs due to fractional frequency synthesis. As a result it provides better resolution for the fraction and avoids any compensation required for correction of the instantaneous jitter","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"320 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128836665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems 用于OFDM系统的高吞吐量，并行，可扩展的LDPC编码器/解码器架构
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321028
Yang Sun, M. Karkooti, Joseph R. Cavallaro
{"title":"High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems","authors":"Yang Sun, M. Karkooti, Joseph R. Cavallaro","doi":"10.1109/DCAS.2006.321028","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321028","url":null,"abstract":"This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype architecture is being implemented on FPGA and tested over the air on our wireless OFDM testbed, which is a highly capable, scalable and extensible platform for advanced wireless research. The ASIC resource requirements of the decoder are reported and a trade-off between pipelined and non-pipelined implementation is described","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131853430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Complete Formal Verification of Multi Core Embedded Systems Using Bounded Model Checking 用有界模型检查完成多核嵌入式系统的形式化验证
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321055
U. Kuhne, D. Grobe, R. Drechsler
{"title":"Complete Formal Verification of Multi Core Embedded Systems Using Bounded Model Checking","authors":"U. Kuhne, D. Grobe, R. Drechsler","doi":"10.1109/DCAS.2006.321055","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321055","url":null,"abstract":"Embedded systems are today frequently used in many applications. Modern designs show a rising complexity, partially including multiple CPU cores. The verification of such systems has to deal with parallel execution of programs and resource conflicts. In this paper we introduce an approach for the formal verification of multi core embedded systems. Bounded model checking is used as the underlying technique. It is shown how it can be applied to the verification of multi core systems ranging from the hardware up to the interaction of multiple cores on the software layer. The approach is demonstrated by the complete verification of a dual core RISC CPU","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127981695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Short distance wireless and its opportunities 短距离无线及其机遇
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321023
J. Rabaey
{"title":"Short distance wireless and its opportunities","authors":"J. Rabaey","doi":"10.1109/DCAS.2006.321023","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321023","url":null,"abstract":"Short distance wireless presents a huge window of opportunity. It needs clear metrics to allow for classification of different approaches in terms of energy and size efficiency. Power and size are dominated by need for precision time and frequency references and can be overcome through innovative system solutions. Short distance wireless may ultimately lead to novel computation and communication models.","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116855844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Technique for Device Stress Relief in CMOS Class-E RF Power Amplifiers CMOS e类射频功率放大器器件应力消除技术
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software Pub Date : 2006-10-01 DOI: 10.1109/DCAS.2006.321046
Xin Wang, Chih-Kai Kang, R. Gharpurey
{"title":"A Technique for Device Stress Relief in CMOS Class-E RF Power Amplifiers","authors":"Xin Wang, Chih-Kai Kang, R. Gharpurey","doi":"10.1109/DCAS.2006.321046","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321046","url":null,"abstract":"Class-E power amplifiers are widely used especially for constant envelope modulation applications due to their high efficiency even for switching signals with slow rise/fall edges. However, they have been rarely used in CMOS process for very high power levels, resulting from their intrinsic poorer power output capability. In this paper, we propose a unique way to control the drain voltage stress of the active switch device when the rise/fall edges of the driving signal occupy a significant portion of the switching cycle. Our approach employs internal signals within a differential amplifier by inserting a transformer between the two active device branches. Depending on specific process and power supply levels, the stress can be relieved up to more than 20%, which gives significant room for either higher power level and efficiency or using faster (and therefore easier to breakdown) devices","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127193270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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