{"title":"Boolean Function Matching using Walsh Spectral Decision Diagrams","authors":"J. Moore, K. Fazel, M. Thornton, D.M. Miller","doi":"10.1109/DCAS.2006.321050","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321050","url":null,"abstract":"This paper investigates two approaches for Boolean matching using NPN equivalence matching. Luks' hypergraph method is implemented and compared to the Walsh spectral decision diagram (SDD) method that we propose here. Both methods determine a canonical representation for each NPN equivalence class. The target functions are then transformed into a canonical representation and compared to the representative canonical forms for the NPN classes. This paper presents the implementation and results of the spectral method in detail. It is shown that the spectral method compares favorably to Luks' method and is better in terms of computational requirements for large functions","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122140963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel Voltage-Mode Structurely Allpass Filters Without External Passive Components","authors":"N. Tarim, F. Golcuk, O. Cicekoglu, H. Kuntman","doi":"10.1109/DCAS.2006.321043","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321043","url":null,"abstract":"In this work, two voltage-mode filters, a first-order and a second-order structurely allpass filter, realized with active components only, are presented. The circuits employ only operational transconductance amplifiers (OTA) and internally compensated operational amplifiers (OA). The second-order filter parameters are independently adjustable. Simulation results are included to verify theory","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123828597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Grand Challenge: The Future of CMOS System-on-Chip Hardware and Software Application Development","authors":"B. Von Herzen, M. Lerer","doi":"10.1109/DCAS.2006.321032","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321032","url":null,"abstract":"CMOS technology trends are forcing system designers to use multiple processors on a single die to meet power performance objectives. Power performance optimization also leads to heterogeneous combinations of processors, DSP units, ASSPs and FPGAs. Both of these trends exacerbate the crisis in software productivity. New tools, languages and implementation techniques must be utilized to ensure achievement of time-to-market objectives for today's system-on-chip designs. Several examples are included to illustrate the problems, issues and opportunities as systems on chips drive towards hundreds of concurrent processes. These issues and their successful resolution are expected to cut across hardware and software boundaries and pervade the electronics industry as the drive for power performance continues over the coming decade","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127457733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reversible Computing and Truly Adiabatic Circuits: Truly Adiabatic Circuits: The Next Great Challenge for Digital Engineering","authors":"M. Frank","doi":"10.1109/DCAS.2006.321027","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321027","url":null,"abstract":"This paper provides a brief review of the energy dissipation problem in conventional FET-based logic. Some alternative device switching principles that might help with this problem in the relatively near term are described. Fundamental limits to dissipation that apply to any non-energy-recovering digital technology are described. Elements required as part of any long-term solution (i.e. adiabatic switching, reversible logic, and resonant clocking) are discussed","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115903792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"All-Digital PLL with Variable Loop Type Characteristics","authors":"R. Staszewski, J. Wallberg, P. Balsara","doi":"10.1109/DCAS.2006.321047","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321047","url":null,"abstract":"A fully-digital frequency synthesizer for RF wireless applications has recently been proposed. It replaces the conventional VCO with a digitally-controlled oscillator with sufficiently fine frequency resolution. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. In this paper, we present novel techniques used in the all-digital PLL to achieve ultra-fast frequency acquisition of < 50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and GSM radios realized in deep-submicron CMOS","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Supply Voltage Adaptive Low-Power Circuit Design","authors":"S. Kirolos, Y. Massoud","doi":"10.1109/DCAS.2006.321051","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321051","url":null,"abstract":"In this paper, we present a circuit design that is capable of responding to changes in the power supply voltage and adjust the gate size-ratio accordingly for minimum energy operation. The dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation. This translates to maximized noise margins over the whole range of the supply voltage. Simulation results show that the performance of the proposed circuit is superior to fixed gate sizes aimed at fixed supply operation. The proposed adaptive gate circuit design provide up to 6times reduction in the power-delay product in comparison with the fixed size gate","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126810943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Feedforward Interference Cancellation in Narrow-Band Receivers","authors":"R. Gharpurey, S. Ayazian","doi":"10.1109/DCAS.2006.321035","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321035","url":null,"abstract":"Design considerations related to feedforward interference cancellation in a narrow-band receiver are discussed. A design is presented that distributes the noise and linearity requirements across two parallel receiver branches. Simulation results from a 1GHz front-end designed in a UMC-0.13mum CMOS process are presented","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124248982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Kirolos, J. Laska, M. Wakin, M. Duarte, D. Baron, T. Ragheb, Y. Massoud, Richard Baraniuk
{"title":"Analog-to-Information Conversion via Random Demodulation","authors":"S. Kirolos, J. Laska, M. Wakin, M. Duarte, D. Baron, T. Ragheb, Y. Massoud, Richard Baraniuk","doi":"10.1109/DCAS.2006.321036","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321036","url":null,"abstract":"Many problems in radar and communication signal processing involve radio frequency (RF) signals of very high bandwidth. This presents a serious challenge to systems that might attempt to use a high-rate analog-to-digital converter (ADC) to sample these signals, as prescribed by the Shannon/Nyquist sampling theorem. In these situations, however, the information level of the signal is often far lower than the actual bandwidth, which prompts the question of whether more efficient schemes can be developed for measuring such signals. In this paper we propose a system that uses modulation, filtering, and sampling to produce a low-rate set of digital measurements. Our \"analog-to-information converter\" (AIC) is inspired by the theory of compressive sensing (CS), which states that a discrete signal having a sparse representation in some dictionary can be recovered from a small number of linear projections of that signal. We generalize the CS theory to continuous-time sparse signals, explain our proposed AIC system in the CS context, and discuss practical issues regarding implementation","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130134780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic Multi-Point Rational Interpolation for Frequency-Selective Model Order Reduction","authors":"M. Alam, A. Nieuwoudt, Y. Massoud","doi":"10.1109/DCAS.2006.321042","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321042","url":null,"abstract":"As process technology continues to scale into the nanoscale regime and overall system complexity increases, the reduced order modeling of on-chip interconnect plays a crucial role in characterizing VLSI system performance. In this paper, we develop a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order interconnect models that are accurate across a wide-range of frequencies. We dynamically select interpolation point by applying a cubic spline-based algorithm to detect complex regions in the system's frequency response. The results indicate that our method provides greater accuracy than techniques that apply multi-shift Krylov subspace methods with uniform interpolation points","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130310475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mixed-Domain Signal Processing","authors":"Y. Tsividis","doi":"10.1109/DCAS.2006.321024","DOIUrl":"https://doi.org/10.1109/DCAS.2006.321024","url":null,"abstract":"We argue that mixing domains within circuits and systems can result in new possibilities. We have presented several examples of mixed-domain systems. Internally time-varying (but externally time-invariant) circuits can be designed to consume only the minimum power needed for each task at hand. Several techniques have been presented for making this possible, while avoiding output transients. Internally nonlinear (but externally linear) digital filters make possible 1) keeping internal signal strength large, even for small-strength inputs and 2) maximizing signal-to-error ratio for a large range of input signals. Continuous-time DSP may offer certain advantages of digital technology without its drawbacks: 1) fully digital (noise immunity, programmability), 2) no sampling; thus no signal aliasing, 3) smaller in-band quantization error, and 4) power goes down with decreasing input activity. All of the principles discussed are at the early research stage; none has reached commercial feasibility. Thorough experimental validation and application of some of the principles presented are being pursued","PeriodicalId":244429,"journal":{"name":"2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129206197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}