Fractional-N Frequency Synthesizer- A Novel Approach

Abstract

A charge pump free, divider less fractional-N frequency synthesizer is proposed. The goal of this study is to design a wideband PLL by utilizing front-end analog signal processing to extract phase information from sinusoidal references. Compared to conventional charge pump PLLs, the phase information is updated at a faster rate, thus a wider bandwidth (BW) can be achieved. The synthesizer is intended for wireless communication applications. Matlab simulations are used to illustrate how the new PLL architecture works, and where the design challenges reside