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Post-breakdown statistics and acceleration characteristics in high-K dielectric stacks 高k介电堆击穿后统计和加速度特性
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784443
E. Wu, J. Suñé, B. Linder, R. Achanta, B. Li, S. Mittl
{"title":"Post-breakdown statistics and acceleration characteristics in high-K dielectric stacks","authors":"E. Wu, J. Suñé, B. Linder, R. Achanta, B. Li, S. Mittl","doi":"10.1109/IRPS.2011.5784443","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784443","url":null,"abstract":"Contrary to recent claims, experimental results obtained in thin and thick Hafnium-based high-K gate dielectric stacks demonstrate that progressive breakdown is relevant in these insulators. For thin and thick stacks and both in NFETs and PFETs, the residual time distributions are found to be non-Weibull with two regions: a universally shallower slope at long times and a steeper slope at short times. The shallow distributions favour the coexistence of single-spot BD and multiple competing spots in different samples. Contrary to what happens in the case of SiON dielectrics, the final failure distribution is reported to be strongly dependent on the threshold current IF used to define device failure. Also contrary to what found for SiON single-layer dielectrics, the voltage acceleration and temperature activation energy of the residual time is reported to be much stronger than that of the first breakdown time. All these results emphasize the important role of progressive breakdown for high-K reliability assessment methodology.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128138528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Electromigration characterization of lead-free flip-chip bumps for 45nm technology node 45nm技术节点无铅倒装凸点的电迁移特性
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784540
C. Hau-Riege, Y. Yau, N. Yu
{"title":"Electromigration characterization of lead-free flip-chip bumps for 45nm technology node","authors":"C. Hau-Riege, Y. Yau, N. Yu","doi":"10.1109/IRPS.2011.5784540","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784540","url":null,"abstract":"We have conducted electromigration experiments on lead-free SnAg flip-chip bump interconnection for 45nm technology node. We report lifetime distributions, kinetic parameters and intermetallic compound formation. Further, we discuss the impact of Ag-concentration as well as current direction on the electromigration reliability of these flip-chip bumps. Based on these analyses, we conclude that lead-free bumps lead to significantly more robust electromigration reliability than their SnPb counterparts, which render lead-free bumps a suitable replacement for the present and future technology nodes in terms of their current-carrying capability.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122269535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Quantitative, nanoscale free-carrier concentration mapping using terahertz near-field nanoscopy 定量，纳米尺度的自由载流子浓度映射使用太赫兹近场纳米显微镜
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784523
J. Wittborn, R. Weiland, A. Huber, F. Keilmann, R. Hillenbrand
{"title":"Quantitative, nanoscale free-carrier concentration mapping using terahertz near-field nanoscopy","authors":"J. Wittborn, R. Weiland, A. Huber, F. Keilmann, R. Hillenbrand","doi":"10.1109/IRPS.2011.5784523","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784523","url":null,"abstract":"We use ultra-resolving terahertz (THz) near-field microscopy based on THz scattering at atomic force microscope tips to analyze 65-nm technology node transistors. Nanoscale resolution is achieved by THz field confinement at the very tip apex to within 30 nm. Images of semiconductor transistors provide evidence of 40 nm (λ/3000) spatial resolution at 2.54 THz (wavelength λ = 118µm) and demonstrate the simultaneous THz recognition of materials and mobile carriers in a single nanodevice. The mobile carrier contrast can be clearly related to near-field excitation of THz-plasmons in the semiconductor regions. The extraordinary high sensitivity of our microscope provides THz near-field contrasts from less than 100 mobile electrons in the probed volume.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115924774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash 垂直NAND闪存用超薄多晶硅通道的研究
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784464
Bio Kim, Seung-Hyun Lim, Dong Woo Kim, T. Nakanishi, S. Yang, Jae-young Ahn, Hanmei Choi, K. Hwang, Yong-Deuk Ko, C. Kang
{"title":"Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash","authors":"Bio Kim, Seung-Hyun Lim, Dong Woo Kim, T. Nakanishi, S. Yang, Jae-young Ahn, Hanmei Choi, K. Hwang, Yong-Deuk Ko, C. Kang","doi":"10.1109/IRPS.2011.5784464","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784464","url":null,"abstract":"We have investigated thin film transistors (TFTs) with ultra-thin polycrystalline silicon (poly-Si) of 77 Å – 185 Å. The TFT charge transfer characteristics such as ON current and effective mobility are dominated not by the thickness itself but by the grain size of poly-Si channel. When the poly-Si channel thickness is decreased with the same grain size, the sub-threshold TFT characteristics are improved without degradation of ON current and reliability properties. These results give us appropriate criteria to establish an excellent poly-Si channel in vertical NAND flash memory.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131986319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A study of via depletion electromigration with very long failure times 极长失效时间的过耗尽电迁移研究
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784494
Baozhen Li, C. Christiansen, K. Chanda, M. Angyal, J. Oakley
{"title":"A study of via depletion electromigration with very long failure times","authors":"Baozhen Li, C. Christiansen, K. Chanda, M. Angyal, J. Oakley","doi":"10.1109/IRPS.2011.5784494","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784494","url":null,"abstract":"Liner coverage in the via plays a critical role on via depletion EM for dual damascene Cu interconnects. Poor liner coverage at the via bottom often results in early EM fails. On the other hand, if the liner at via bottom is permeable to Cu diffusion, thanks to the constant Cu supply into the via from the line below, a very long or even “immortal” EM failure mode can be observed. This paper discusses how to modulate the Cu diffusion through the via bottom liner and its impact on product reliability.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129965963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Thermomechanical reliability of through-silicon vias in 3D interconnects 三维互连中硅通孔的热机械可靠性
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784487
K. Lu, Suk-kyu Ryu, J. Im, Rui Huang, P. Ho
{"title":"Thermomechanical reliability of through-silicon vias in 3D interconnects","authors":"K. Lu, Suk-kyu Ryu, J. Im, Rui Huang, P. Ho","doi":"10.1109/IRPS.2011.5784487","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784487","url":null,"abstract":"This paper investigates two key aspects of thermomechanical reliability of through-silicon vias (TSV) in 3D interconnects. One is the piezoresistivity effect induced by the near surface stresses on the charge mobility for p- and n- channel MOSFET devices. The other problem concerns the interfacial delamination induced by thermal stresses including the pop-up mechanism of TSV with a ‘nail head’. We first analyze the three-dimensional distribution of the thermal stresses near the TSV and the wafer surface. The stress characteristics are inherently 3D in nature with the near-surface stress distributions distinctly different from the 2D solution. The energy release rate for interfacial delamination of TSV is evaluated under both cooling and heating conditions, using an analytical solution for a steady-state crack growth as an upper bound and numerical solutions by finite element analysis (FEA) for more detailed calculations. Based on these results, we examine the piezoresistivity effect induced by the near surface stresses on the charge mobility for p-and n- channel MOSFET devices, including the study of the effect of TSV scaling on the keep-out zone for MOSFET devices. This is followed by analyzing the energy release rate for interfacial delamiantion for a fully filled TSV and the potential mechanisms for TSV pop-up due to interfacial fracture.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130152583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Novel negative Vt shift program disturb phenomena in 2X∼3X nm NAND flash memory cells 新型负Vt移位程序干扰2X ~ 3X nm NAND闪存单元
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784548
Soonok Seo, Hyungseok Kim, Sungkye Park, Seokkiu Lee, S. Aritome, Sungjoo Hong
{"title":"Novel negative Vt shift program disturb phenomena in 2X∼3X nm NAND flash memory cells","authors":"Soonok Seo, Hyungseok Kim, Sungkye Park, Seokkiu Lee, S. Aritome, Sungjoo Hong","doi":"10.1109/IRPS.2011.5784548","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784548","url":null,"abstract":"A novel program disturb phenomena of “negative” cell-Vt shift has been investigated for the first time in 2X∼3X nm Self-Aligned STI cell[1,2] of NAND flash memory. The negative Vt shift occurs on an inhibited cell adjacent to a cell being programmed in the WL direction. The magnitude of the shift becomes larger when the programming voltage (VPgm) is higher, thinner field oxide and slower program speed of the adjacent cell. The mechanism of negative Vt shift is attributed to hot holes that are generated by FN electrons, injected from channel / junction to the control gate (CG) along the isolation. This phenomenon will become worse with scaling since hot hole generation is increased by increasing electron injection due to narrower FG space. Therefore, this negative Vt shift phenomenon is one of the new NAND flash memory cell scaling limiter, that needs to be managed for 2bits and 3bits/cell in 2X nm and beyond.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134474558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Multiple cell upsets tolerant content-addressable memory 多单元扰乱容忍内容可寻址内存
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784594
Syed Mohsin Abbas, S. Baeg, Sungju Park
{"title":"Multiple cell upsets tolerant content-addressable memory","authors":"Syed Mohsin Abbas, S. Baeg, Sungju Park","doi":"10.1109/IRPS.2011.5784594","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784594","url":null,"abstract":"Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. It has been previously proposed that Hamming distance based approaches are good for SCUs but are not effective for MCUs. These schemes require a large number of extra parity bits for mitigating MCUs, and so they are not a practical solution for CAM devices. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123707503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Understanding of traps causing random telegraph noise based on experimentally extracted time constants and amplitude 基于实验提取的时间常数和振幅，了解引起随机电报噪声的陷阱
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784503
K. Abe, A. Teramoto, S. Sugawa, T. Ohmi
{"title":"Understanding of traps causing random telegraph noise based on experimentally extracted time constants and amplitude","authors":"K. Abe, A. Teramoto, S. Sugawa, T. Ohmi","doi":"10.1109/IRPS.2011.5784503","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784503","url":null,"abstract":"We develop a high-speed method to extract time constants and noise amplitude of random telegraph noise (RTN). We investigate distributions of these RTN parameters for more than 270 n- and p-MOSFETs and clarify spectroscopy of traps causing RTN. Most of traps are distributed in an energy range of 220 meV, and mean times to capture/emission are measured in a wide range between 10 µs and 20 ms.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127448087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Investigation of multistage linear region drain current degradation and gate-oxide breakdown under hot-carrier stress in BCD HV PMOS 热载子应力下BCD高压PMOS的多级线性区域漏极电流退化和栅极氧化物击穿研究
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784515
Yu-Hui Huang, J. Shih, C.C. Liu, Y. Lee, R. Ranjan, P. Chiang, Dah-Chuen Ho, Kenneth Wu
{"title":"Investigation of multistage linear region drain current degradation and gate-oxide breakdown under hot-carrier stress in BCD HV PMOS","authors":"Yu-Hui Huang, J. Shih, C.C. Liu, Y. Lee, R. Ranjan, P. Chiang, Dah-Chuen Ho, Kenneth Wu","doi":"10.1109/IRPS.2011.5784515","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784515","url":null,"abstract":"Hot-carrier injection (HCI) at maximum gate current (IG) stress condition for BCD HVPMOS has been studied. It is found that HCI not only causes linear region drain current degradation and minimizes the operation window, but also degrades the gate oxide (GOX) and may result in GOX breakdown. A multistage IDlin degradation behavior has been observed during HCI stress, which is associated with two competing mechanisms, i.e., interface-state (Nit) generation and electron trapping caused by hot electrons originated from impact ionization. HCI leads to the gate oxide breakdown even at very low e-field of ∼1.5MV/cm across the GOX. TCAD simulation results by placing Nit and negative charges at different location of the device also support a multistage IDlin degradation. It is found that both initial IG and bulk current (IB) are well correlated with GOX time-dependent-dielectric-breakdown (TDDB). In addition, better TDDB has been observed at higher temperature compared to lower temperature, which verifies that GOX breakdown is associated with HCI.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127348422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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