2011 International Reliability Physics Symposium最新文献_第3页

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs 32nm高k/金属栅极cmosfet中频率相关的TDDB行为及其可靠性鉴定

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784445

Kyongtaek Lee, J. Nam, M. Jin, Kidan Bae, Junekyun Park, Lira Hwang, Jungin Kim, H. Kim, Jongwoo Park

{"title":"Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs","authors":"Kyongtaek Lee, J. Nam, M. Jin, Kidan Bae, Junekyun Park, Lira Hwang, Jungin Kim, H. Kim, Jongwoo Park","doi":"10.1109/IRPS.2011.5784445","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784445","url":null,"abstract":"The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (tbd) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, tbd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter tbd than with DC at a lower frequency. This is attributed to hole trapping into IL as Vg is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer tbd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because Gm degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129090775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

A study of the influence of high voltage device characteristics by electron beam irradiation during nanoprobing 电子束辐照对纳米探测过程中高压器件特性影响的研究

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784575

H. Lin

引用次数: 0

Performance and structure degradations of SiGe HBT after electromagnetic field stress 电磁场应力作用下SiGe HBT的性能和结构退化

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784555

A. Alaeddine, M. Kadi, K. Daoud

引用次数: 3

Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects 电迁移电阻增强与cop或CuMn为先进的铜互连

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784493

C. Christiansen, Baozhen Li, M. Angyal, T. Kane, V. McGahay, Y. Wang, Shaoning Yao

{"title":"Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects","authors":"C. Christiansen, Baozhen Li, M. Angyal, T. Kane, V. McGahay, Y. Wang, Shaoning Yao","doi":"10.1109/IRPS.2011.5784493","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784493","url":null,"abstract":"Suppressing Cu diffusion along the Cu/Cap interface has proven to be one of the most effective ways to enhance the electromigration (EM) resistance of advanced Cu interconnects. Two methods, depositing a thin layer of CoWP on the Cu surface and doping the Cu seed layer with Mn, are presented in this paper. While each effectively enhanced the EM performance, they behaved somewhat differently in improving the line-depletion and via-depletion EM performance. CoWP functioned primarily as a Cu surface modifier and did not alter the Cu diffusion behavior below the surface, making Cu interconnects capped with CoWP very sensitive to defects in the via. As a result, the hardware processed with CoWP had greatly increased EM failure times, but also had large variability in failure times and activation energy. On the other hand, the hardware with the CuMn seed layer relied on Mn segregation to the Cu surface to slow down the Cu diffusion, plus Mn also may have diffused to grain boundaries and defective areas of the liner. Although the EM failure times of Cu interconnects with CuMn seed in some cases were not as long as those with CoWP, the variability and sensitivity to process defects was reduced.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123268064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Impact of ion-induced transients on high-speed dual-complementary Flip-Flop designs 离子诱导瞬态对高速双互补触发器设计的影响

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784600

D. Black, R. Reed, W. H. Robinson, J. Black, D. Limbrick, Kevin D. Dick

引用次数: 1

Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process 嵌入式高压CMOS工艺中低触发高保持电压的改进ESD保护结构设计

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784505

T. Lai, Lu-An Chen, Tien-Hao Tang, K. Su

引用次数: 2

Electromigration failure mechanisms for different flip chip bump configurations 不同倒装芯片碰撞配置的电迁移失效机制

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784541

R. Labie, T. Webers, C. Winters, V. Cherman, K. Croes, B. Vandevelde, F. Dosseul

{"title":"Electromigration failure mechanisms for different flip chip bump configurations","authors":"R. Labie, T. Webers, C. Winters, V. Cherman, K. Croes, B. Vandevelde, F. Dosseul","doi":"10.1109/IRPS.2011.5784541","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784541","url":null,"abstract":"Different flip chip bump configurations are investigated in terms of their electromigration behavior. Standard SAC (SnAgCu) solder bumps with a Ni/Au finish on the chip side are compared with Cu pillar bumps soldered with a thin layer of SnAg alloy. The substrate finish is identical for both cases and consists of a 17µm thick Cu layer. Depending on the current direction, different interfaces are stressed what results in variable degradation mechanisms. Both the 17µm thick Cu UBM and the Cu pillar bumps outperform the Ni/Au chip finish due to the fast formation of an intermetallic phase which covers the full solder stand-off height. The excessive intermetallic growth indicates significant Cu dissolution but void formation couldn't be detected. When the electrons are forced from the Ni/Au finish to the solder bump, micro-structural degradation and an according bump resistance increase can be clearly monitored for different test conditions. The electromigration parameters of Black's acceleration model are defined for the Ni/Au UBM. A TaN temperature sensor is incorporated in the test chip which allows in-situ measurements of the actual device temperature. In this way, the generated Joule heating can be clearly monitored.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133088080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Identification, characterization, and implications of shadow degradation in thin film solar cells 薄膜太阳能电池中阴影降解的鉴定、表征和意义

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784535

S. Dongaonkar, M. Alam, Y. Karthik, S. Mahapatra, Dapeng Wang, M. Frei

引用次数: 25

Application of reliability test standards to SiC Power MOSFETs 可靠性测试标准在SiC功率mosfet中的应用

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784573

R. Green, A. Lelis, D. Habersat

{"title":"Application of reliability test standards to SiC Power MOSFETs","authors":"R. Green, A. Lelis, D. Habersat","doi":"10.1109/IRPS.2011.5784573","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784573","url":null,"abstract":"The application of existing reliability test standards, based on Si technology, to SiC power MOSFET reliability qualification can in some cases result in ambiguous test results. Depending on the exact measurement procedure, a given device stress tested under identical conditions may either pass or fail. The large variations observed in ID-VGS characteristics, and accompanying shift in threshold voltage (VT) and change in leakage current, are likely due to the complex time, temperature, and bias dependent nature of the charging and discharging of significant numbers of near-interfacial oxide traps (and possibly mitigated by the movement of mobile ions) which are not present in Si power devices. The variation in VT following a high temperature gate-bias (HTGB) stress is shown to be dependent on the measurement delay time, sweep direction, and temperature. Negative gate-bias temperature stress results show that device reliability may be limited due to increased drain leakage current in the OFF-state, which is caused by large shifts in VT depending on the gate-bias stress time, bias magnitude, and stress temperature. In addition, positive gate-bias stressing at elevated temperature may increase power dissipation in the ON-state.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 64

Effects of BTI during AHTOL on SRAM VMIN AHTOL时BTI对SRAM VMIN的影响

2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784460

Sun-Me Lim, Heebum Hong, Sunil Yu, Zhang Ming, Jongwoo Park, Yongshik Kim

{"title":"Effects of BTI during AHTOL on SRAM VMIN","authors":"Sun-Me Lim, Heebum Hong, Sunil Yu, Zhang Ming, Jongwoo Park, Yongshik Kim","doi":"10.1109/IRPS.2011.5784460","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784460","url":null,"abstract":"We present an optimal method to characterize and mitigate SRAM Vmin shift during Accelerated High Temperature Operating Life (AHTOL) stress test while taking PG BTI effect into account. Prior work has reported that changes in SRAM VMIN during AHTOL stress test have a strong dependency on Bias Temperature Instability (BTI) degradation on PD and PU transistors [1, 2]. In this work, we have found that PG transistor BTI at a practical duty cycle can appreciably alter SRAM VMIN shift during AHTOL. We have expanded SRAM VMIN shift model on the basis of PG BTI as well as PD and PU BTIs. Statistical SRAM cell design with Response Surface Methodology (RSM)/Response Optimize (RO), Z-score method, is used to extract Optimal Z-score Ridge (OZR). OZR provides the optimal SRAM VMIN at both T0 and EOL. Our work has shown that BTI vector with PD, PG, and PU BTI components should be placed on the OZR in VT domain to mitigate VMIN shift during AHTOL. The proposed theory has been confirmed with model-hardware correlation of individual disturbance-/writability-limited VMIN degradations. With a consideration of OZR and BTI vector, we can achieve almost zero VMIN shift of SRAM macro during AHTOL in gate-first high-k metal gate 32nm process.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131836832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8