Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process

Abstract

The modified ESD protection structure with N-well implant in the drain region has been proposed and investigated in this paper. Table I lists the comparison of TLP, HBM/MM ESD robustness, and TLU immunity between HV GGNMOS structure with and without N-well implant. By the influence of N-well implant, many drawbacks such as double snapback, soft leakage degradation, non-uniform current conduction, low ESD robustness, and weak TLU immunity in the common HV GGNMOS device are overcome efficaciously. Without additional mask or process cost, the proposed ESD device with low trigger voltage and high holding voltage is effectively employed for power clamp protection in HV CMOS ICs without latchup or transient-induced latchup damage.