Effects of BTI during AHTOL on SRAM VMIN

We present an optimal method to characterize and mitigate SRAM Vmin shift during Accelerated High Temperature Operating Life (AHTOL) stress test while taking PG BTI effect into account. Prior work has reported that changes in SRAM VMIN during AHTOL stress test have a strong dependency on Bias Temperature Instability (BTI) degradation on PD and PU transistors [1, 2]. In this work, we have found that PG transistor BTI at a practical duty cycle can appreciably alter SRAM VMIN shift during AHTOL. We have expanded SRAM VMIN shift model on the basis of PG BTI as well as PD and PU BTIs. Statistical SRAM cell design with Response Surface Methodology (RSM)/Response Optimize (RO), Z-score method, is used to extract Optimal Z-score Ridge (OZR). OZR provides the optimal SRAM VMIN at both T0 and EOL. Our work has shown that BTI vector with PD, PG, and PU BTI components should be placed on the OZR in VT domain to mitigate VMIN shift during AHTOL. The proposed theory has been confirmed with model-hardware correlation of individual disturbance-/writability-limited VMIN degradations. With a consideration of OZR and BTI vector, we can achieve almost zero VMIN shift of SRAM macro during AHTOL in gate-first high-k metal gate 32nm process.