R. Labie, T. Webers, C. Winters, V. Cherman, K. Croes, B. Vandevelde, F. Dosseul
{"title":"Electromigration failure mechanisms for different flip chip bump configurations","authors":"R. Labie, T. Webers, C. Winters, V. Cherman, K. Croes, B. Vandevelde, F. Dosseul","doi":"10.1109/IRPS.2011.5784541","DOIUrl":null,"url":null,"abstract":"Different flip chip bump configurations are investigated in terms of their electromigration behavior. Standard SAC (SnAgCu) solder bumps with a Ni/Au finish on the chip side are compared with Cu pillar bumps soldered with a thin layer of SnAg alloy. The substrate finish is identical for both cases and consists of a 17µm thick Cu layer. Depending on the current direction, different interfaces are stressed what results in variable degradation mechanisms. Both the 17µm thick Cu UBM and the Cu pillar bumps outperform the Ni/Au chip finish due to the fast formation of an intermetallic phase which covers the full solder stand-off height. The excessive intermetallic growth indicates significant Cu dissolution but void formation couldn't be detected. When the electrons are forced from the Ni/Au finish to the solder bump, micro-structural degradation and an according bump resistance increase can be clearly monitored for different test conditions. The electromigration parameters of Black's acceleration model are defined for the Ni/Au UBM. A TaN temperature sensor is incorporated in the test chip which allows in-situ measurements of the actual device temperature. In this way, the generated Joule heating can be clearly monitored.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2011.5784541","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Different flip chip bump configurations are investigated in terms of their electromigration behavior. Standard SAC (SnAgCu) solder bumps with a Ni/Au finish on the chip side are compared with Cu pillar bumps soldered with a thin layer of SnAg alloy. The substrate finish is identical for both cases and consists of a 17µm thick Cu layer. Depending on the current direction, different interfaces are stressed what results in variable degradation mechanisms. Both the 17µm thick Cu UBM and the Cu pillar bumps outperform the Ni/Au chip finish due to the fast formation of an intermetallic phase which covers the full solder stand-off height. The excessive intermetallic growth indicates significant Cu dissolution but void formation couldn't be detected. When the electrons are forced from the Ni/Au finish to the solder bump, micro-structural degradation and an according bump resistance increase can be clearly monitored for different test conditions. The electromigration parameters of Black's acceleration model are defined for the Ni/Au UBM. A TaN temperature sensor is incorporated in the test chip which allows in-situ measurements of the actual device temperature. In this way, the generated Joule heating can be clearly monitored.