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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)最新文献

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Random testing of multi-port static random access memories 多端口静态随机存取存储器的随机测试
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029770
F. Karimi, F. Meyer, F. Lombardi
{"title":"Random testing of multi-port static random access memories","authors":"F. Karimi, F. Meyer, F. Lombardi","doi":"10.1109/MTDT.2002.1029770","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029770","url":null,"abstract":"This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams. In the state diagrams, transition probabilities are established by considering the effects of the memory operations (read and write), the lines involved in the fault (bit and word-lines) as well as the types and number of ports. Test lengths per cell at 99.9% coverage are given.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125716662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch 用于100gb /s STS-1交换机的9端口SRAM的设计和测试
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029767
R. Gibbins, R. Adams, Thomas J. Eckenrode, M. Ouellette, Yuejian Wu
{"title":"Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch","authors":"R. Gibbins, R. Adams, Thomas J. Eckenrode, M. Ouellette, Yuejian Wu","doi":"10.1109/MTDT.2002.1029767","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029767","url":null,"abstract":"This paper presents the design, fault modeling, and BIST solution of an application specific 9-port SRAM. The use of the 9-port SRAM in place of more conventional memory in a 100 Gb/s SONET switch ASIC resulted in calculated reductions of 43% in die size, 31% in power consumption and 75% in data memory bit count. A custom programmable BIST solution was implemented that takes into consideration the memory's special features such as the large number of ports, large read-to-write port asymmetry and the TDM read scheme.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114709783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fault modeling technique to test memory BIST algorithms 一种测试内存BIST算法的故障建模技术
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029771
R. Venkatesh, S. Sushanth Kumar, J. Philip, Sunil Shukla
{"title":"A fault modeling technique to test memory BIST algorithms","authors":"R. Venkatesh, S. Sushanth Kumar, J. Philip, Sunil Shukla","doi":"10.1109/MTDT.2002.1029771","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029771","url":null,"abstract":"The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory built-in-self-test (BIST) logic assumes utmost importance amongst all on chip self test logic. Therefore the BIST logic should be comprehensively validated before fabrication. The key to this achievement lies in a robust memory fault model. In this paper we propose a novel fault modeling technique. This technique can scale to emulate any kind of memory architecture currently in use. The memory architecture and the location of any fault that can occur in the cell array are represented in terms of equations. The technique applies these equations and calculates an address where the fault can be modeled.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116289380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Converting an embedded low-power SRAM from bulk to PD-SOI 将嵌入式低功耗SRAM从bulk转换为PD-SOI
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029780
M. Casu, P. Flatresse
{"title":"Converting an embedded low-power SRAM from bulk to PD-SOI","authors":"M. Casu, P. Flatresse","doi":"10.1109/MTDT.2002.1029780","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029780","url":null,"abstract":"The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13/spl mu/m bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131991357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new single ended sense amplifier for low voltage embedded EEPROM non volatile memories 一种用于低压嵌入式EEPROM非易失性存储器的新型单端感测放大器
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029776
Caroline Papaix, J. Daga
{"title":"A new single ended sense amplifier for low voltage embedded EEPROM non volatile memories","authors":"Caroline Papaix, J. Daga","doi":"10.1109/MTDT.2002.1029776","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029776","url":null,"abstract":"A new single ended sense amplifier is presented in this paper. It is based on a very simple direct current-voltage conversion. It has been designed in standard CMOS process for embedded non-volatile memories. Its performances are compared to one of the actually most integrated sense amplifiers, based on differential structures. A 40% faster access time has been obtained at 1.8V.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123715063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Fast and compact error correcting scheme for reliable multilevel flash memories 可靠的多电平快闪记忆体快速、紧凑的纠错方案
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029759
Daniele Rossi, C. Metra, B. Riccò
{"title":"Fast and compact error correcting scheme for reliable multilevel flash memories","authors":"Daniele Rossi, C. Metra, B. Riccò","doi":"10.1109/MTDT.2002.1029759","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029759","url":null,"abstract":"This paper presents a method to reduce area and timing overhead due to the implementation of standard single symbol correcting codes to provide ML flash memories with error correction capability. In particular, the proposed method is based on the manipulation of the parity check matrix which defines a code, which allows one to minimize the matrix weight and the maximum row weight. Furthermore, we show that a minimal increase in the redundancy, with respect to the standard case, allows a further considerable reduction of the impact on the memory access time, as well as on the area overhead due to the error correction circuitry.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121555175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios 不同冗余场景下嵌入式sram的硅基良率增益评估方法
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-08 DOI: 10.1109/MTDT.2002.1029764
E. Rondey, Yann Tellier, Simone Borri
{"title":"A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios","authors":"E. Rondey, Yann Tellier, Simone Borri","doi":"10.1109/MTDT.2002.1029764","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029764","url":null,"abstract":"Yield improvement is an essential issue for modem high-volume manufacturing CMOS processes. Process yield is particularly low for area-critical designs, such as embedded memories. The use of redundancy structures which replace faulty memory locations with good ones, has a direct impact on the final chip yield. This paper describes an experimental methodology employed to evaluate the yield gain associated with different redundancy approaches and shows how this method can be applied to determine the optimal redundancy configuration which maximizes the number of good dies per wafer, depending on the embedded memory requirements of a specific product.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116198842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A scan-BIST environment for testing embedded memories 用于测试嵌入式存储器的扫描- bist环境
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-08 DOI: 10.1109/MTDT.2002.1029758
F. Karimi, F. Lombardi
{"title":"A scan-BIST environment for testing embedded memories","authors":"F. Karimi, F. Lombardi","doi":"10.1109/MTDT.2002.1029758","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029758","url":null,"abstract":"This paper presents a new IEEE 1149.1 compatible architecture as an intermediate environment for testing embedded memories. A BIST structure and a boundary scan are used for testing various memory configurations for programmability as well as improved controllability and observability. Its novelty is that features such as modularity, scalability with word size and adaptability to different memory configurations and testing requirements, are accomplished at relative ease. In the boundary scan, user-defined test modes are utilized so that basic modifications to the elements of a seed algorithm can be generated very efficiently.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115710991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A simulator for evaluating redundancy analysis algorithms of repairable embedded memories 一种评估可修嵌入式存储器冗余分析算法的模拟器
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-08 DOI: 10.1109/MTDT.2002.1029766
Rei-Fu Huang, Jin-Fu Li, J. Yeh, Cheng-Wen Wu
{"title":"A simulator for evaluating redundancy analysis algorithms of repairable embedded memories","authors":"Rei-Fu Huang, Jin-Fu Li, J. Yeh, Cheng-Wen Wu","doi":"10.1109/MTDT.2002.1029766","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029766","url":null,"abstract":"We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115989417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A March-based fault location algorithm for static random access memories 基于march的静态随机存储器故障定位算法
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 1900-01-01 DOI: 10.1109/MTDT.2002.1029765
V. Vardanian, Y. Zorian
{"title":"A March-based fault location algorithm for static random access memories","authors":"V. Vardanian, Y. Zorian","doi":"10.1109/MTDT.2002.1029765","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029765","url":null,"abstract":"A March-based fault location algorithm is proposed for the repair of word-oriented static RAMs. A March CL algorithm of complexity 12N, N is the number of memory words, is defined for fault detection and partial diagnosis. A 3N or 4N March-like algorithm is used for location of the aggressor words of inter-word state, idempotent, inversion, write-disturb coupling faults (CF). Then another March-like algorithm of complexity 9(1+logB), B is the number of bits in the word, is applied to locate the aggressor bit in the aggressor word. Finally, a March algorithm of complexity 6(1+logB)N is used to detect and locate intra-word stuck-at, transition faults, as well as CFs. The proposed algorithm has higher fault location ability and lower time complexity than other known algorithms developed for fault location in SRAMs.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115297557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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