A fault modeling technique to test memory BIST algorithms

Abstract

The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory built-in-self-test (BIST) logic assumes utmost importance amongst all on chip self test logic. Therefore the BIST logic should be comprehensively validated before fabrication. The key to this achievement lies in a robust memory fault model. In this paper we propose a novel fault modeling technique. This technique can scale to emulate any kind of memory architecture currently in use. The memory architecture and the location of any fault that can occur in the cell array are represented in terms of equations. The technique applies these equations and calculates an address where the fault can be modeled.