Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)

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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) - 最新文献

Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC)

Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029778 Thierry Devoivre, M. Lunenborg, C. Julien, J. Carrere, P. Ferreira, W. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond

Decreasing EEPROM programming bias with negative voltage, reliability impact

Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029781 R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, J. Mirabel

March SS: a test for all static simple RAM faults

Pub Date : 2002-07-10 DOI: 10.1109/MTDT.2002.1029769 S. Hamdioui, A. V. Goor, M. Rodgers

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