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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)最新文献

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Fault tolerant insertion and verification: a case study 容错插入和验证:一个案例研究
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 1900-01-01 DOI: 10.1109/MTDT.2002.1029762
A. Manzone, Diego De Costantini
{"title":"Fault tolerant insertion and verification: a case study","authors":"A. Manzone, Diego De Costantini","doi":"10.1109/MTDT.2002.1029762","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029762","url":null,"abstract":"The particular circuit structures that allow the building of a fault tolerant (FT) circuit have been extensively studied in the past, but currently there is a lack of CAD support in the design and evaluation of FT circuits. The aim of the AMATISTA European project (IST project 11762) is to develop a set of tools devoted to the design of FT digital circuits. The toolset is composed of: an automatic insertion tool and a simulation tool to validate the FT design. This paper is a case study describing how this set of FTI (fault tolerant insertion) and FTV (fault tolerant verification) tools have been used to increase the reliability in a typical automotive application.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124868972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defect-oriented analysis of memory BIST tests 面向缺陷的记忆类BIST测试分析
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 1900-01-01 DOI: 10.1109/MTDT.2002.1029756
A. Jee
{"title":"Defect-oriented analysis of memory BIST tests","authors":"A. Jee","doi":"10.1109/MTDT.2002.1029756","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029756","url":null,"abstract":"This paper describes a defect-oriented analysis of 4 BIST tests that are used to test a commercial 6-port embedded SRAM. We examine the realistic fault and defect coverages of these memory BIST tests. We also uncover the subtle effect that addressing order has on the coverage that a test can provide. In addition, we show that the coverage that a test provides can vary from row to row depending on the addressing scheme.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114285361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design and implementation of a self-checking scheme for railway trackside systems 铁路轨旁系统自检方案的设计与实现
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 1900-01-01 DOI: 10.1109/MTDT.2002.1029763
L. Schiano, C. Metra, Diego Marino
{"title":"Design and implementation of a self-checking scheme for railway trackside systems","authors":"L. Schiano, C. Metra, Diego Marino","doi":"10.1109/MTDT.2002.1029763","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029763","url":null,"abstract":"We propose the self-checking design of the transmission and reception blocks of a trackside control system used for railway applications. Our scheme has been conceived for field-programmable gate arrays. A prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements. Our scheme negligibly impacts system's performance and features self-checking ability with respect to a wide set of possible internal faults, representative of the most likely faults for FPGA-implemented systems.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132996791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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