面向缺陷的记忆类BIST测试分析

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 1900-01-01 DOI:10.1109/MTDT.2002.1029756

A. Jee

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引用次数: 10

摘要

本文描述了用于测试商用6端口嵌入式SRAM的4个BIST测试的缺陷导向分析。我们考察了这些内存测试的实际错误和缺陷覆盖率。我们还揭示了寻址顺序对测试所能提供的覆盖率的微妙影响。此外，我们还展示了测试提供的覆盖率可以随寻址方案的不同而变化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Defect-oriented analysis of memory BIST tests

This paper describes a defect-oriented analysis of 4 BIST tests that are used to test a commercial 6-port embedded SRAM. We examine the realistic fault and defect coverages of these memory BIST tests. We also uncover the subtle effect that addressing order has on the coverage that a test can provide. In addition, we show that the coverage that a test provides can vary from row to row depending on the addressing scheme.

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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)

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