铁路轨旁系统自检方案的设计与实现

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 1900-01-01 DOI:10.1109/MTDT.2002.1029763

L. Schiano, C. Metra, Diego Marino

{"title":"铁路轨旁系统自检方案的设计与实现","authors":"L. Schiano, C. Metra, Diego Marino","doi":"10.1109/MTDT.2002.1029763","DOIUrl":null,"url":null,"abstract":"We propose the self-checking design of the transmission and reception blocks of a trackside control system used for railway applications. Our scheme has been conceived for field-programmable gate arrays. A prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements. Our scheme negligibly impacts system's performance and features self-checking ability with respect to a wide set of possible internal faults, representative of the most likely faults for FPGA-implemented systems.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design and implementation of a self-checking scheme for railway trackside systems\",\"authors\":\"L. Schiano, C. Metra, Diego Marino\",\"doi\":\"10.1109/MTDT.2002.1029763\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose the self-checking design of the transmission and reception blocks of a trackside control system used for railway applications. Our scheme has been conceived for field-programmable gate arrays. A prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements. Our scheme negligibly impacts system's performance and features self-checking ability with respect to a wide set of possible internal faults, representative of the most likely faults for FPGA-implemented systems.\",\"PeriodicalId\":230758,\"journal\":{\"name\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.2002.1029763\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029763","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

提出了一种用于铁路应用的轨旁控制系统的发送和接收模块的自检设计。我们的方案是为现场可编程门阵列设计的。实现了样机，并通过布局后仿真和实验测量验证了样机的正确性。我们的方案对系统性能的影响可以忽略不计，并且具有针对广泛的可能的内部故障的自检能力，这些故障代表了fpga实现系统中最可能出现的故障。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design and implementation of a self-checking scheme for railway trackside systems

We propose the self-checking design of the transmission and reception blocks of a trackside control system used for railway applications. Our scheme has been conceived for field-programmable gate arrays. A prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements. Our scheme negligibly impacts system's performance and features self-checking ability with respect to a wide set of possible internal faults, representative of the most likely faults for FPGA-implemented systems.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)

自引率

0.00%

发文量