Defect-oriented analysis of memory BIST tests

Abstract

This paper describes a defect-oriented analysis of 4 BIST tests that are used to test a commercial 6-port embedded SRAM. We examine the realistic fault and defect coverages of these memory BIST tests. We also uncover the subtle effect that addressing order has on the coverage that a test can provide. In addition, we show that the coverage that a test provides can vary from row to row depending on the addressing scheme.