{"title":"容错插入和验证:一个案例研究","authors":"A. Manzone, Diego De Costantini","doi":"10.1109/MTDT.2002.1029762","DOIUrl":null,"url":null,"abstract":"The particular circuit structures that allow the building of a fault tolerant (FT) circuit have been extensively studied in the past, but currently there is a lack of CAD support in the design and evaluation of FT circuits. The aim of the AMATISTA European project (IST project 11762) is to develop a set of tools devoted to the design of FT digital circuits. The toolset is composed of: an automatic insertion tool and a simulation tool to validate the FT design. This paper is a case study describing how this set of FTI (fault tolerant insertion) and FTV (fault tolerant verification) tools have been used to increase the reliability in a typical automotive application.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fault tolerant insertion and verification: a case study\",\"authors\":\"A. Manzone, Diego De Costantini\",\"doi\":\"10.1109/MTDT.2002.1029762\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The particular circuit structures that allow the building of a fault tolerant (FT) circuit have been extensively studied in the past, but currently there is a lack of CAD support in the design and evaluation of FT circuits. The aim of the AMATISTA European project (IST project 11762) is to develop a set of tools devoted to the design of FT digital circuits. The toolset is composed of: an automatic insertion tool and a simulation tool to validate the FT design. This paper is a case study describing how this set of FTI (fault tolerant insertion) and FTV (fault tolerant verification) tools have been used to increase the reliability in a typical automotive application.\",\"PeriodicalId\":230758,\"journal\":{\"name\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"volume\":\"87 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.2002.1029762\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fault tolerant insertion and verification: a case study
The particular circuit structures that allow the building of a fault tolerant (FT) circuit have been extensively studied in the past, but currently there is a lack of CAD support in the design and evaluation of FT circuits. The aim of the AMATISTA European project (IST project 11762) is to develop a set of tools devoted to the design of FT digital circuits. The toolset is composed of: an automatic insertion tool and a simulation tool to validate the FT design. This paper is a case study describing how this set of FTI (fault tolerant insertion) and FTV (fault tolerant verification) tools have been used to increase the reliability in a typical automotive application.