将嵌入式低功耗SRAM从bulk转换为PD-SOI

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI:10.1109/MTDT.2002.1029780

M. Casu, P. Flatresse

{"title":"将嵌入式低功耗SRAM从bulk转换为PD-SOI","authors":"M. Casu, P. Flatresse","doi":"10.1109/MTDT.2002.1029780","DOIUrl":null,"url":null,"abstract":"The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13/spl mu/m bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Converting an embedded low-power SRAM from bulk to PD-SOI\",\"authors\":\"M. Casu, P. Flatresse\",\"doi\":\"10.1109/MTDT.2002.1029780\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13/spl mu/m bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.\",\"PeriodicalId\":230758,\"journal\":{\"name\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.2002.1029780\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029780","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文描述了用于低功耗应用的嵌入式1 Mbit SRAM从0.13/spl mu/m体积到部分耗尽绝缘体上硅(PDSOI)技术的迁移。浮体效应如阈值电压变化和寄生双极打开及其对感测放大器、基于通闸的多路复用器和动态解码器的影响。讨论了在特定部位使用身体接触等解决方案。一个具有各种可测试配置的SRAM芯片已经被贴出。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Converting an embedded low-power SRAM from bulk to PD-SOI

The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13/spl mu/m bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.

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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)

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