Random testing of multi-port static random access memories

Abstract

This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams. In the state diagrams, transition probabilities are established by considering the effects of the memory operations (read and write), the lines involved in the fault (bit and word-lines) as well as the types and number of ports. Test lengths per cell at 99.9% coverage are given.