用于100gb /s STS-1交换机的9端口SRAM的设计和测试

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) Pub Date : 2002-07-10 DOI:10.1109/MTDT.2002.1029767

R. Gibbins, R. Adams, Thomas J. Eckenrode, M. Ouellette, Yuejian Wu

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引用次数: 3

摘要

本文介绍了一种特定应用的9端口SRAM的设计、故障建模和BIST解决方案。在100 Gb/s SONET开关ASIC中，使用9端口SRAM代替更传统的内存，计算结果是芯片尺寸减少43%，功耗减少31%，数据存储位数减少75%。考虑到存储器的特殊特性，如大量端口、大读写端口不对称和TDM读取方案，实现了一个定制的可编程BIST解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch

This paper presents the design, fault modeling, and BIST solution of an application specific 9-port SRAM. The use of the 9-port SRAM in place of more conventional memory in a 100 Gb/s SONET switch ASIC resulted in calculated reductions of 43% in die size, 31% in power consumption and 75% in data memory bit count. A custom programmable BIST solution was implemented that takes into consideration the memory's special features such as the large number of ports, large read-to-write port asymmetry and the TDM read scheme.

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Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)

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