Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch

Abstract

This paper presents the design, fault modeling, and BIST solution of an application specific 9-port SRAM. The use of the 9-port SRAM in place of more conventional memory in a 100 Gb/s SONET switch ASIC resulted in calculated reductions of 43% in die size, 31% in power consumption and 75% in data memory bit count. A custom programmable BIST solution was implemented that takes into consideration the memory's special features such as the large number of ports, large read-to-write port asymmetry and the TDM read scheme.