{"title":"Converting an embedded low-power SRAM from bulk to PD-SOI","authors":"M. Casu, P. Flatresse","doi":"10.1109/MTDT.2002.1029780","DOIUrl":null,"url":null,"abstract":"The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13/spl mu/m bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029780","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13/spl mu/m bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.