Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium最新文献

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A parametric study of flip chip reliability based on solder fatigue modelling 基于焊料疲劳模型的倒装芯片可靠性参数化研究
S. Popelar
{"title":"A parametric study of flip chip reliability based on solder fatigue modelling","authors":"S. Popelar","doi":"10.1109/IEMT.1997.626935","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626935","url":null,"abstract":"A solder fatigue model for 63Sn/Pb solder has been developed by combining nonlinear finite element modelling with thermal fatigue data of assorted flip chip assemblies. The model characterizes the creep fatigue phenomena of the solder alloy by correlating the amount of creep strain energy dissipated per thermal cycle with the characteristic Weibull life of the critical solder joint. It has been validated for various die sizes, bump geometries, board materials and thermal profiles. Furthermore, the model has accurately predicted fatigue lives for flip chip assemblies with and without underfill. The solder fatigue model has been utilized to investigate the reliability of flip chip joints subjected to thermal cycling. In particular, a parametric study had been performed which shows how various flip chip design parameters will affect solder joint fatigue. Finite element models have been developed to analyze the effect of die size, die thickness, solder joint height, cap diameter and underfill properties on solder fatigue. For this investigation, all analyses have been carried out for parts on ceramic substrates. The results for underfilled parts show that while die size does not influence solder joint reliability, the effects of underfill CTE are very important. Non-underfilled parts are significantly influenced by die size, cap size and joint height.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121983768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
Optimizing stencil printing parameters for organic materials 有机材料模板打印参数优化
T. Jiang, S. S. Ahmad, C. Jesse, W. Moden
{"title":"Optimizing stencil printing parameters for organic materials","authors":"T. Jiang, S. S. Ahmad, C. Jesse, W. Moden","doi":"10.1109/IEMT.1997.626878","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626878","url":null,"abstract":"Effect of printing speed and squeegee pressure were studied for the quality of stencil printed organic material using a commercially available statistical application, JMP(R). Prints were evaluated by measuring their actual widths compared to the stencil opening in both parallel and perpendicular directions relative to squeegee travel; by print wall angle; film thickness and the extent of material bleed.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125528232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Web-based tools in support of life cycle engineering of telecommunications products 支持电信产品生命周期工程的基于web的工具
P. J. Palmer, David J. Williams, A. C. Dixon
{"title":"Web-based tools in support of life cycle engineering of telecommunications products","authors":"P. J. Palmer, David J. Williams, A. C. Dixon","doi":"10.1109/IEMT.1997.626889","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626889","url":null,"abstract":"This paper illustrates the use of the internet in life cycle engineering. Two demonstration tools that have been constructed to assist life cycle engineering within a large organisation are presented. The tools have been designed to run in a local, intranet or internet environment and serve to demonstrate how HTML based documents are a versatile method for presenting information or providing applications that must be generally available.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121322060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automated adaptive control of the reflow soldering of electronic assemblies 电子组件回流焊的自动自适应控制
P. Conway, D. Whalley, M. Wilkinson, D.J. Williams
{"title":"Automated adaptive control of the reflow soldering of electronic assemblies","authors":"P. Conway, D. Whalley, M. Wilkinson, D.J. Williams","doi":"10.1109/IEMT.1997.626923","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626923","url":null,"abstract":"This paper describes a new technique for the monitoring and automated control of the reflow soldering process. The new technique combines state of the art infra-red (IR) sensor technology, coupled with application specific process control software, to provide a unique capability to both monitor actual product temperatures during the soldering process and to use this information to modify the process settings. The development of techniques to allow rapid variation of the heat transfer from the oven to the in-process Printed Circuit Assemblies (PCAs) allows the system to automatically adjust the soldering oven's process settings for each individual PCA passing through it. This product-by-product profiling facilitates the assurance of consistent thermal histories and also allows the oven to optimise its energy consumption to the demands of each product. Archiving of the reflow temperature profiles also provides full traceability to the reflow process. The incorporation of IR sensing technology also aids in determining/verifying the oven profile at the introduction of new PCA designs. This paper presents an overview of the construction and operation of the system and outlines the technical challenges that have been met and overcome.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131481806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Automated isostatic lamination of green sheets in multilayer electric components 多层电子元件中绿片的自动等静压层压
K. Kaminaga
{"title":"Automated isostatic lamination of green sheets in multilayer electric components","authors":"K. Kaminaga","doi":"10.1109/IEMT.1997.626926","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626926","url":null,"abstract":"Isostatic (hydraulic) pressing with a warm temperature has laminated ceramics green sheets in multilayer electric components such as IC packages, capacitors, etc. in more uniform and higher density than other methods such as mechanical presses. This results in higher throughput because the deviated or low density of laminated green sheets may cause delamination and uneven shrinkage in the sintering process. Isostatic pressing, however, has two problems due to the wet bag process. 1. Vapor generation - during heating up, binder and plasticizer in the sheets inside a bag are vaporized and the vapor is collected in the bag which may aggravate the uniformity of the laminating pressure on the sheets. 2. Automation - the operation may not be fully automated due to the handling of a wet bag. This paper introduces the essential solution for these two remaining problems.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132339094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Assessment of failure rate of printed board assemblies by the high temperature accelerated life test 用高温加速寿命试验评估印制板组件的故障率
Choong-Reol Young, J. Yoo
{"title":"Assessment of failure rate of printed board assemblies by the high temperature accelerated life test","authors":"Choong-Reol Young, J. Yoo","doi":"10.1109/IEMT.1997.626864","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626864","url":null,"abstract":"In this paper, we summarize the work in the field of assessing the reliability of printed board assemblies of a switching system, applying the method of the high temperature accelerated life-test. A test for reliability assessment of printed board assemblies having many different kinds of components in a large variety of complexity is very important to classify the failures. We calculate the acceleration factor of taking into consideration of the complexity of a printed board assembly. An actual accelerated test with accelerated factors obtained by the Arrhenius are conducted with 30 samples during two months. Test result are analyzed applying the Weibull-log linear model. The analysis show that the design characteristics are adequate to satisfy the requirement of reliability.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131242012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of tapeless lead-on-chip (LOC) packaging process with i-line photosensitive polyimide i线光敏聚酰亚胺无带片上铅封装工艺的发展
M. Amagai, T. Saitoh, M. Ohsumi, E. Kawasaki, C. Yew, L. Chye, J. Toh, Swee Yang Khim
{"title":"Development of tapeless lead-on-chip (LOC) packaging process with i-line photosensitive polyimide","authors":"M. Amagai, T. Saitoh, M. Ohsumi, E. Kawasaki, C. Yew, L. Chye, J. Toh, Swee Yang Khim","doi":"10.1109/IEMT.1997.626924","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626924","url":null,"abstract":"A double-sided adhesive tape is typically used as an insulator and mechanical buffer layer between the chip and lead frame in lead-on-chip (LOC) packages. The costs associated with the lead frame and tape process make the current LOC package more expensive than conventional packaging. A new tapeless LOC package process has been developed which significantly reduces the production costs. In this new process, the tape is replaced by a i-line photosensitive thermosetting polyimide layer coated on the passivation deposited wafer. This paper describes the optimum material properties for the polyimide, the fabrication process parameters, and the experimental and simulated reliability and performance results of the tapeless LOC package.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123150440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Method of dynamically determining cycle time of a working stage 动态确定工作阶段周期时间的方法
Tza-Huei Wang, Kuo-Cheng Lin, Seng-Rong Huang
{"title":"Method of dynamically determining cycle time of a working stage","authors":"Tza-Huei Wang, Kuo-Cheng Lin, Seng-Rong Huang","doi":"10.1109/IEMT.1997.626952","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626952","url":null,"abstract":"This paper presents a method of predicting production cycle time of a working stage in semiconductor manufacturing. For Scheduling, cycle time of a stage is usually applied to estimate the cycle time of the entire production line or the remaining production time. It is also often applied to generate the reasonable inventory level that should be queued in front of a stage. Since cycle time is highly affected by equipment loading density, a model is first created by combining Little's formula and Kingman's equation in the queuing theory to relate loading density with it. Cycle time distribution of each stage over the past time is characterized as a parameter set, based on the cycle time model and using a plurality of prior associated data. The equipment loading density of a stage in the next production run is calculated by considering the demanded quantity, mix and process flows of products. The stage cycle time of the next production run is then predicted by applying the equipment loading density to the cycle time model. The optimum amount of inventory kept in front of a stage to prevent equipment staving or WIP (work in process) piling up is also determined by using the data of cycle time and production target of a stage. The cycle time and the optimum inventory level (which is called standard WIP) of a stage are dynamically tuned as the customers' demands vary. With this, cycle time and standard WIP could be more precisely defined and the delivery would be well controlled.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125937829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fracture mechanics analysis of the popcorn cracking in the plastic IC packages 塑料IC封装爆裂的断裂力学分析
Y. Park, Jin Yu
{"title":"A fracture mechanics analysis of the popcorn cracking in the plastic IC packages","authors":"Y. Park, Jin Yu","doi":"10.1109/IEMT.1997.626866","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626866","url":null,"abstract":"Popcorn cracking phenomenon in surface mounted packages is treated by assuming an inherent edge crack at the die pad/EMC interface of a TQFP and subsequent interface delamination under thermal and/or vapor pressure loadings. Using the finite element methods and the methods of interface fracture mechanics, path independent energy release rate is calculated and compared to the interface toughness which is assumed to be a function of the phase angle. Results indicate that the edge crack propagates toward the center leading to the delamination of the entire die pad/EMC interface most notably for the vapor pressure loading, then mixed loading when thermal and vapor pressure loadings are applied simultaneously. For the thermal loading, only the cooling process is likely to lead to the entire delamination where both the energy release rate and interface toughness decrease with the crack length. For the vapor pressure loading, the energy release rate increases parabolically with the crack length but proportionally with the vapor pressure while the interface toughness remains almost constant. In the case of the mixed loading, the energy release rate increases as in the vapor pressure loading, but the interface toughness decreases with the crack length; Stress states near the crack tip were closer to mode II for thermal loading but to mode I for vapor pressure loading, and changed from mode II to mode I with the crack length for the mixed loading.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127035230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Test chip development to support standardization efforts 测试芯片开发以支持标准化工作
B. Bright
{"title":"Test chip development to support standardization efforts","authors":"B. Bright","doi":"10.1109/IEMT.1997.626900","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626900","url":null,"abstract":"A test chip has been developed which integrates test structures for performing reliability testing, and thermal and electrical characterization on packages and assembly processes. This work supports test chip standardization efforts of the Semiconductor Assembly Council (SAC) and the JEDEC JC15 Electrical Measurements and Simulation committee. For the purpose of reliability qualifications, several single-metal structures are provided to evaluate the environmental integrity of the package. Characterization structures, such as a capacitor for moisture monitoring, a strain gauge rosette, diodes, a heating resistor, and custom digital drivers have been integrated to quantify the mechanical, thermal, and electrical performance aspects of the package. This paper provides an overview of the test die functionality and discusses the application of each test sensor.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"370 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133081250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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