{"title":"The design and implementation of NASA's advanced flight computing module","authors":"L. Alkalaj, B. Jarvis","doi":"10.1109/MCMC.1995.512001","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512001","url":null,"abstract":"This paper describes the first MCM module of the AFC program which implements the functionality of a 32-bit RISC radiation hardened space flight computer. This module was designed jointly by engineers at JPL and TRW using a collaborative partnership agreement. The MCM was fabbed at nCHIP Corporation. The AFC program also plans to design, develop, and fab two more MCM modules: the Mass Memory MCM, and Programmable I/O MCM. These three MCMs will then be stacked as part of a scalable (stackable) core avionics architecture. The flight computer MCM described in this pager contains 33 die in a single 2 by 4 inch AlN package from Coors, with a total of 442 pins. The MCM uses nCHIP's die stack approach for both SRAM and EEPROM.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129119604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wire width optimization of transmission lines for low power design","authors":"Rohinish Gupta, J. Willis, L. Pillage","doi":"10.1109/MCMC.1995.512015","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512015","url":null,"abstract":"With potentially denser and larger circuits for the emerging multi-chip module technologies, the problem of signal integrity and power dissipation is of paramount importance. This paper addresses the issue of low-power design of MCM interconnects in conjunction with the problem of signal integrity. A termination strategy is presented that uses width optimization of interconnects to size drivers and interconnects on MCM's such that signal quality is preserved, delay constraints are met, and a low-power design is achieved. The optimization algorithm accounts for the nonlinear effect of drivers via a linearized model to facilitate an efficient transmission line synthesis. Further, it is demonstrated that the low-power design algorithm converges to a globally optimal solution.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129641870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient modeling and simulation of coupled transmission lines","authors":"E. C. Chang, S. Kang","doi":"10.1109/MCMC.1995.512019","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512019","url":null,"abstract":"We present a computationally efficient method to simulate transmission lines. Based on the generalized method of characteristics, transmission lines are modeled with characteristic impedances and waveform generators. Thus the first major task involves network synthesis. The second is efficient computation of the synthesized waveform generators which requires computationally expensive convolution integral evaluation during transient simulation of transmission lines. As solutions of the above tasks, we present iterative linear least square fitting (ILLSF) for the first task and PRC for the second. The superior performance of ILLSF and the efficiency of PRC will be demonstrated for the transient simulation of coupled transmission lines.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130657014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Avoiding dispersion in distributed RLC lines by shaping","authors":"J. Roychowdhury","doi":"10.1109/MCMC.1995.512013","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512013","url":null,"abstract":"The shaping of RLC lines for delay reduction is investigated. It is shown that inductance can act to diminish dispersion, to the extent of reducing delay to its theoretical time-of-flight minimum even in the presence of substantial loss in the line. Simulations predict significant delay improvement (25%-38%) for long MCM lines propagating high-speed signals.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127933757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A silicon-on-silicon MCM for voice recognition/telephone answering device","authors":"B. J. Han, S. Das, R. Frye, K. Tai, M. Lau","doi":"10.1109/MCMC.1995.512002","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512002","url":null,"abstract":"We have built and demonstrated a silicon-on-silicon multichip module for use in a cellular telephone. This module performs speaker-dependent voice recognition and also serves as a telephone answering device. It takes advantage of the miniaturization possible with MCM technology. Other important factors in the use of this approach are the fast design and fabrication cycle and the ability to readily integrate specialized CMOS processes into a single package.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128195409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A unified approach to chip, test, and assembly technologies for MCMs","authors":"D. Bartelink","doi":"10.1109/MCMC.1995.512031","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512031","url":null,"abstract":"The \"post-fab\" manufacturing technologies of test, assembly and packaging are taking a larger share of the final cost of complex ICs than ever before even though the cost of a wafer fab sits at unprecedented levels. These technologies have been allowed to remain static as long as they were minor cost adders, but now they need to receive the same attention in technology evolution as their better known wafer-fab rivals. The traditional approaches to packaging and test have been optimized independently of each other and of chip technology. This paper provides a re-examination of current practice and proposes a step-by-step plan toward a joint optimum for meeting the fab and post-fab constraints for high-performance microprocessor ICs. This optimum considers the fact that, particularly at high operating speeds, chips must be electrically exercised as part of their manufacture both to ensure rapid yield learning and to guarantee Known Good Die specifications.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130623874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sensitivity analysis of interconnect networks based on S-parameter macromodel","authors":"Yanhua Sun, W. Dai","doi":"10.1109/MCMC.1995.512009","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512009","url":null,"abstract":"In this paper a simple and efficient approach for time domain sensitivity analysis is presented. Since moments of the Taylor series of a function are derivatives of the function to frequency, the same technique can be used to compute sensitivities. The basic elements in the linear networks are described by their S-parameters and the first derivatives to parameter variations of the S-parameter; which are expressed as Taylor series. A linear network is reduced to an S-parameter based macromodel together with the driving sources and the nodes of interest. The network transfer functions together with their sensitivities with respect to all the parameter variations can be obtained in one pass during the network reduction process. Since the number of external nodes are much less than the total number of nodes in the network, this method is very efficient The method can be extended to compute the second or higher order sensitivities, which are very difficult, if not impossible, for other known methods. Experimental results show that this method is robust and efficient. This method is very useful for performance optimization, especially when the number of design variables and number of specifications are very large.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121634103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A physics-of-failure (POF) approach to addressing device reliability in accelerated testing of MCMs","authors":"J. Evans, M. Cushing, P. Lall, R. Bauernschub","doi":"10.1109/MCMC.1995.511998","DOIUrl":"https://doi.org/10.1109/MCMC.1995.511998","url":null,"abstract":"The physics-of-failure testing approach for multichip modules presented in this paper determines test levels based on failure mechanisms, failure modes, and stresses for the application. It uses quantitative failure models and acceleration transforms and adapts the knowledge of dominant failure mechanisms to the selection of accelerating stress parameters. The stress levels, designed specifically for each test article, are based on manufacturing processes, geometry, and materials.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134038877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermosonic bonding for flip-chip assembly","authors":"S. Kang, T. McLaren, Wenge Zhang, Y.C. Lee","doi":"10.1109/MCMC.1995.512007","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512007","url":null,"abstract":"Thermosonic flip-chip bonding is a new, solderless technology for area-array connections. Its simple, clean, and dry process may significantly reduce the assembly cost for prototyping and manufacturing of MCMs. The feasibility of the technology has been demonstrated by our studies on 64-I/O GaAs-on-silicon test vehicles. But, the repeatability of the bonding quality needs to be controlled. Two process control variables, force and ultrasonic power applied to the chip, will be discussed.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114418325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel 2-sided multi-chip-module used to create a 50,000 gate programmable logic device","authors":"R. Terrill","doi":"10.1109/MCMC.1995.512004","DOIUrl":"https://doi.org/10.1109/MCMC.1995.512004","url":null,"abstract":"A 32-layer ceramic multi-chip-module was created to support a 50,000-gate programmable logic device. The high gate-count was achieved by combining four 12,500-gate PLDs and one programmable interconnect on both sides of a 32-layer ceramic substrate. A known-good-die process has been developed for one of the active components by using the module itself as a test bed. In addition, an assembly process has been developed which maximizes rework yield. Made possible with MCM technology, this high-density device is intended for gate array prototyping.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}