The design and implementation of NASA's advanced flight computing module

Abstract

This paper describes the first MCM module of the AFC program which implements the functionality of a 32-bit RISC radiation hardened space flight computer. This module was designed jointly by engineers at JPL and TRW using a collaborative partnership agreement. The MCM was fabbed at nCHIP Corporation. The AFC program also plans to design, develop, and fab two more MCM modules: the Mass Memory MCM, and Programmable I/O MCM. These three MCMs will then be stacked as part of a scalable (stackable) core avionics architecture. The flight computer MCM described in this pager contains 33 die in a single 2 by 4 inch AlN package from Coors, with a total of 442 pins. The MCM uses nCHIP's die stack approach for both SRAM and EEPROM.