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Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)最新文献

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A CMOS current divider CMOS电流分压器
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-28 DOI: 10.1109/MMICA.1999.833578
F. Devos, C. Taillefer, C. Wang, M. Ahmad, M. Swamy
{"title":"A CMOS current divider","authors":"F. Devos, C. Taillefer, C. Wang, M. Ahmad, M. Swamy","doi":"10.1109/MMICA.1999.833578","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833578","url":null,"abstract":"In this article, a simple circuit is proposed to implement the division of one current by another. This circuit is composed of two MOS transistors, a voltage comparator, and two capacitors. The divider operates well in a weak current range. Using a 1.5 /spl mu/m single-poly CMOS technology, the proposed circuit occupies a silicon area of approximately 30 /spl mu/m/spl times/40 /spl mu/m.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116220447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated vision system: object detection and localization 综合视觉系统:目标检测与定位
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-28 DOI: 10.1109/MMICA.1999.833613
R. Reyna, D. Esteve, D. Martinez
{"title":"An integrated vision system: object detection and localization","authors":"R. Reyna, D. Esteve, D. Martinez","doi":"10.1109/MMICA.1999.833613","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833613","url":null,"abstract":"Several industrial and research activities are demanding more robust and efficient image processing systems. Whether they are discrete systems exploiting the capacities of the latest processors and algorithms in the market, or whether they are integrated systems exploiting the advancements in technology: compactness, low power and speed. This paper describes a real-time vision integrated system for object recognition, based in an APS CMOS matrix. The aim of this work is to demonstrate that we can take some decisions on the fly of the reading process in order to locate and identify objects within the entire image matrix. A neural network circuit will implement the decision subsystem.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134478147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
DFT and on-line test of high-performance data converters: a practical case DFT与高性能数据转换器的在线测试:一个实际案例
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-28 DOI: 10.1109/MMICA.1999.833602
E. Peralías, A. Rueda, J. A. Prieto, J. Huertas
{"title":"DFT and on-line test of high-performance data converters: a practical case","authors":"E. Peralías, A. Rueda, J. A. Prieto, J. Huertas","doi":"10.1109/MMICA.1999.833602","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833602","url":null,"abstract":"This paper discusses a Design-for-Testability (DFT) technique applicable to pipelined Analog-to-Digital Converters (ADC). The objective of this DFT is to improve both the on- and off-line testability of these important mixed-signal ICs.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128784452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A CMOS low-jitter phase frequency detector for giga-bit/s clock recovery 用于千兆位/秒时钟恢复的CMOS低抖动相位频率检测器
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-28 DOI: 10.1109/MMICA.1999.833606
H. Wang, R. Nottenburg
{"title":"A CMOS low-jitter phase frequency detector for giga-bit/s clock recovery","authors":"H. Wang, R. Nottenburg","doi":"10.1109/MMICA.1999.833606","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833606","url":null,"abstract":"The PFD consists of a bang-bang Frequency Detector (FD) and a Phase Detector (PD) with analog outputs. The frequency acquisition range is over /spl plusmn/30%. The bang-bang FD disconnects itself from the loop once lock acquisition is achieved. The PFD was fabricated in a 0.5 /spl mu/m CMOS process for 1 Gbit/s clock recovery. RMS jitter in the recovered 1 GHz clock is 7.4 ps.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125400326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A folded-cascode OTA based on complementary differential-pairs for HF applications 高频应用中基于互补差分对的折叠级联码OTA
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-28 DOI: 10.1109/MMICA.1999.833595
G. Olivera-Romero, J. Silva-Martínez
{"title":"A folded-cascode OTA based on complementary differential-pairs for HF applications","authors":"G. Olivera-Romero, J. Silva-Martínez","doi":"10.1109/MMICA.1999.833595","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833595","url":null,"abstract":"In this paper, several previously reported folded-cascode Operational Transconductance Amplifiers (OTAs) and a proposed structure based on complementary differential pairs are compared. For the same power consumption and similar transistor dimensions the proposed OTA presents both higher bandwidth and faster response. It is shown that for a typical switched-capacitor integrator, using 0.5 pF capacitors, 1% settling times below to 3 ns can be achieved.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127468925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Analog processing for nonlinear fuzzy controller development 用于模拟处理的非线性模糊控制器的开发
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833625
J. Castillo, W. Martinez, M. Banuelos, J. Pérez, F. Lara-Rosano, J. Valeriano, S. Quintana
{"title":"Analog processing for nonlinear fuzzy controller development","authors":"J. Castillo, W. Martinez, M. Banuelos, J. Pérez, F. Lara-Rosano, J. Valeriano, S. Quintana","doi":"10.1109/MMICA.1999.833625","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833625","url":null,"abstract":"In this work we present some analog circuits used in fuzzy control. We have done some modifications to conventional implementations and we present a new circuit for the inference stage. We have substituted the conventional method of rule aggregation for a simpler one, which results in a reduced number of transistors. We also present an example of an analog fuzzy controller applied to a nonlinear plant with multiplicity of stable and unstable equilibrium points, different operation regions and different operation modes.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"17 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123028573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Adaptive analog timer for on-chip testing 自适应模拟定时器片上测试
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833587
B. Provost, E. Sánchez-Sinencio
{"title":"Adaptive analog timer for on-chip testing","authors":"B. Provost, E. Sánchez-Sinencio","doi":"10.1109/MMICA.1999.833587","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833587","url":null,"abstract":"A practical approach for generating precise and slow analog ramps to be used for on-chip time-domain analog testing and for monotonicity and histogram test of ADCs is introduced. The calibration uses a discrete-time adaptive scheme. Two implementations of the approach are proposed; one is continuous-time and the second is discrete-time. Convergence criteria are defined. Results from a fabricated circuit in a low-cost 2 /spl mu/m technology are in agreement with theoretical results.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125868994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Novel digital techniques to improve the sensitivity of limiting amplifier 提高限幅放大器灵敏度的新型数字技术
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833634
Yang-Han Lee, Kuo-Ting Lin
{"title":"Novel digital techniques to improve the sensitivity of limiting amplifier","authors":"Yang-Han Lee, Kuo-Ting Lin","doi":"10.1109/MMICA.1999.833634","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833634","url":null,"abstract":"In this paper we utilize the novel digital techniques (TW, DRMC, DS) to improve the sensitivity of the limiting amplifier. The Time Window (TW) technique can ignore the positive and negative trigger noises within the window close time. The Delay Racing Memory Counter (DRMC) technique can eliminate the positive trigger noises within the window open time. The Delay Sum (DS) technique can solve the negative trigger noise around the signal transition from low to high. The experimental results are also presented.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121733552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Amplifier design for fast settling performance 放大器设计，快速沉降性能
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833594
Yiqin Chen, M. Schlarmann, R. Geiger
{"title":"Amplifier design for fast settling performance","authors":"Yiqin Chen, M. Schlarmann, R. Geiger","doi":"10.1109/MMICA.1999.833594","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833594","url":null,"abstract":"A design strategy for minimizing a feedback amplifier's step-response settling time is introduced. Central to this approach is the clear identification of the independent design parameters characterizing the amplifier and the introduction of a figure of merit for assessing the settling performance of an amplifier that is independent of power, supply voltage and capacitive loading. With this approach, the settling performance of a given amplifier architecture can be optimized and the relative performance of different amplifier architectures can be assessed. Emphasis in this paper is on the two-stage operational amplifier architecture but the technique readily extends to other widely used operational amplifier structures.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129374281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SC implementation of FIR filters for digital communication systems 数字通信系统中FIR滤波器的SC实现
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833629
J. M. Rocha-Pérez, J. Silva-Martínez
{"title":"SC implementation of FIR filters for digital communication systems","authors":"J. M. Rocha-Pérez, J. Silva-Martínez","doi":"10.1109/MMICA.1999.833629","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833629","url":null,"abstract":"In this paper a Switched-Capacitor (SC) architecture for the processing of binary input signals is presented. The architecture is especially useful for the realization of Finite Impulse Response (FIR) filters. A 23-th order Raised-Cosine (RC) filter employing 11 capacitors is designed. The filter has been simulated using a 0.8 /spl mu/m analog CMOS process. Hspice results have shown the feasibility of the proposed design technique.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130872464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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