A CMOS low-jitter phase frequency detector for giga-bit/s clock recovery

Abstract

The PFD consists of a bang-bang Frequency Detector (FD) and a Phase Detector (PD) with analog outputs. The frequency acquisition range is over /spl plusmn/30%. The bang-bang FD disconnects itself from the loop once lock acquisition is achieved. The PFD was fabricated in a 0.5 /spl mu/m CMOS process for 1 Gbit/s clock recovery. RMS jitter in the recovered 1 GHz clock is 7.4 ps.