用于千兆位/秒时钟恢复的CMOS低抖动相位频率检测器

Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-28 DOI:10.1109/MMICA.1999.833606

H. Wang, R. Nottenburg

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引用次数: 1

摘要

PFD由具有模拟输出的bang-bang频率检测器(FD)和相位检测器(PD)组成。频率采集范围超过/spl + /30%。一旦锁获取完成，bang-bang FD将自己从循环中断开。在0.5 /spl mu/m CMOS工艺下制备PFD，时钟恢复速率为1 Gbit/s。恢复的1ghz时钟的RMS抖动为7.4 ps。

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A CMOS low-jitter phase frequency detector for giga-bit/s clock recovery

The PFD consists of a bang-bang Frequency Detector (FD) and a Phase Detector (PD) with analog outputs. The frequency acquisition range is over /spl plusmn/30%. The bang-bang FD disconnects itself from the loop once lock acquisition is achieved. The PFD was fabricated in a 0.5 /spl mu/m CMOS process for 1 Gbit/s clock recovery. RMS jitter in the recovered 1 GHz clock is 7.4 ps.

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Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)

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