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Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)最新文献

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Preliminary discussion of a world-wide-web based analog circuit design tool and design knowledge repository 基于万维网的模拟电路设计工具及设计知识库的初步探讨
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833596
M. Schlarmann, R. Geiger
{"title":"Preliminary discussion of a world-wide-web based analog circuit design tool and design knowledge repository","authors":"M. Schlarmann, R. Geiger","doi":"10.1109/MMICA.1999.833596","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833596","url":null,"abstract":"A prototype network-centric circuit design tool and design knowledge repository has been developed. It allows a designer with network access to interactively explore a circuit design space of pre-characterized circuit topologies using a convenient graphical user interface. Any user can extend the system to include new or custom circuit topologies without a lot of programming effort by writing their own design specification files. Designers will benefit from the use of the application as it will enable them to obtain a deeper understanding of the operation of their circuits and the performance tradeoffs that are possible for pre-characterized circuit topologies. The enhanced understanding gained by the designers will result in better design realizations and will accelerate the development of improved topologies in the future. Several benefits accrue due to the use of the network-centric computing paradigm of which the most significant is the enhanced communication of design knowledge and prevention of reinvention by the use of a centralized design knowledge repository.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130054326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Substrate noise analysis for RF CMOS mixers based on state equation technique 基于状态方程技术的射频CMOS混频器衬底噪声分析
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833607
L. Li, J. Guo, Zheying Li, H. Teuhunen
{"title":"Substrate noise analysis for RF CMOS mixers based on state equation technique","authors":"L. Li, J. Guo, Zheying Li, H. Teuhunen","doi":"10.1109/MMICA.1999.833607","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833607","url":null,"abstract":"Mixers are analysed as a linear periodic time-varying (LPTV) system with large LO signal excitation and without small-signal excitation. Efficient simulation of the mixed-signal substrate coupling is possible using macromodels of RF circuits. The substrate noise is added as a small signal disturbance via a coupling contact. A technique using a simple and systematic engineering approach to analyse the impact of the substrate coupling in a mixed-signal RF CMOS mixer is presented.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121964841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced two-graph theory for symbolic analysis of electrical networks 电网符号分析的增强双图理论
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833591
R. Giomi, A. Luchetta
{"title":"Enhanced two-graph theory for symbolic analysis of electrical networks","authors":"R. Giomi, A. Luchetta","doi":"10.1109/MMICA.1999.833591","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833591","url":null,"abstract":"In this paper a new method is described to completely solve in symbolic form an electrical analog network. The technique is an extension of the two-graph one, which has been shown to be the most suitable method for symbolic analysis of large analog circuits. On the other hand an attempt has been made to overcome the RLC-g/sub m/ limitation still inherent in the classical application of the algorithm.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126712677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A transition based BIST technique for mixed-signal VLSI circuits 混合信号VLSI电路中基于转换的BIST技术
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833588
A. Walker, P. Lala
{"title":"A transition based BIST technique for mixed-signal VLSI circuits","authors":"A. Walker, P. Lala","doi":"10.1109/MMICA.1999.833588","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833588","url":null,"abstract":"A new mixed-signal built-in self-test approach that is based upon voltage transitions at the primary output of the analog block under test (ABUT) is presented in this paper. This ABUT output is the pulse response of the ABUT for a rail-to-rail pulse stream. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) or/and digital-to-analog converter(DAC). This approach also does not require any additional analog circuits to realize the test signal generator and sample circuits. The paper is concluded with an example of the application of the proposed approach for a passive lowpass filter.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131841296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing switched-current memory cells using DC stimuli 使用直流刺激测试开关电流记忆单元
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833586
M. Renovell, F. Azais, J.-C. Bodin, Y. Bertrand
{"title":"Testing switched-current memory cells using DC stimuli","authors":"M. Renovell, F. Azais, J.-C. Bodin, Y. Bertrand","doi":"10.1109/MMICA.1999.833586","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833586","url":null,"abstract":"The authors study the efficiency of a DC test for a memory cell, which is the elementary building block for switched-current circuits. Simulations are performed on two different cells. It is demonstrated that most of the hard faults are detected using one single input test current for the basic cascode memory cell, and two reverse-sign currents for the S/sup 2/I cascode memory cell. This study is also extended taking into account different values for the short and open resistance.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Two level performance estimator for high level synthesis of analog integrated circuits with feedback 带反馈的模拟集成电路高电平合成的二电平性能估计
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833626
A. Núñez-Aldana, R. Vemuri
{"title":"Two level performance estimator for high level synthesis of analog integrated circuits with feedback","authors":"A. Núñez-Aldana, R. Vemuri","doi":"10.1109/MMICA.1999.833626","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833626","url":null,"abstract":"In this paper, we present a technique for estimating the gain, bandwidth, power and area of analog integrated circuits. A two-step approach is adopted to speed up the estimation process and handle larger analog systems. In the first step, the performance of basic analog components is estimated using a knowledge-based approach. Then, component models are generated with the estimates produced at this phase. In the second phase, we use a symbolic analysis methodology to evaluate the performance at the system level. The system net-list is represented by a signal flow graph (SFG) using the component models generated at the previous phase. The SFG approach allows one to handle feedback loops at the system level.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132166898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis of switched capacitor filters in a multi-level optimization environment 多层优化环境下开关电容滤波器的合成
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833628
G. Alpaydin, G. Erten, S. Balkır, G. Dundar
{"title":"Synthesis of switched capacitor filters in a multi-level optimization environment","authors":"G. Alpaydin, G. Erten, S. Balkır, G. Dundar","doi":"10.1109/MMICA.1999.833628","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833628","url":null,"abstract":"In this paper, the synthesis of switched capacitor (SC) filters in a multi-level optimization environment is presented. The environment is based on a high level optimizer and a circuit level optimizer. The non-idealities of the SC building blocks are considered at high level and incorporated as macromodels. This enables the accurate estimation of filter parameters which are passed to the circuit level optimizer for transistor level synthesis. The optimization strategy at circuit level combines evolution strategies with simulated annealing in finding the global optimum solution. The algorithmic details of the synthesis system are discussed and illustrated examples that demonstrate the validity of the approach are presented.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124844498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of domino CMOS cells under delay constraint 延迟约束下的多米诺CMOS电池设计
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833610
A. Zamudio, V. Champac, A. Sarmiento-Reyes
{"title":"Design of domino CMOS cells under delay constraint","authors":"A. Zamudio, V. Champac, A. Sarmiento-Reyes","doi":"10.1109/MMICA.1999.833610","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833610","url":null,"abstract":"Simple expressions to estimate the delay and power consumption of domino gates have been developed. Using these expressions design guidelines are established for domino cells under a specified delay. It has been found that there is a trade-off between the power consumption and noise margin for domino cells designed for a specified delay. A good correspondence exists between the theoretical and simulated results.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128072970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel basis of dynamical systems and its application to desampling 动力系统的新基础及其在解采样中的应用
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833600
T. Yamawaki
{"title":"A novel basis of dynamical systems and its application to desampling","authors":"T. Yamawaki","doi":"10.1109/MMICA.1999.833600","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833600","url":null,"abstract":"This paper provides a novel basis of dynamical systems. The basis involves a new signal space consisting of real-valued signals and discrete moment signals expressed by real time functions and delta function series, respectively, a notation of uniform rate sampling in the space, a method to distinguish among system classes, novel names of conceivable sorts of dynamical linear or discretely linear systems and a unified representation of these systems. To demonstrate the availability of the basis, a system model, with sampling, of a 0-th order hold element is shown and extended to those of approximate circuits of ideal low-pass filters. Finally, conventional sampled-data system models of interpolating circuits are denied because of false counter-examples of Shannon's sampling theorem.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122863050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A clock and data recovery IC for communications and radar applications 用于通信和雷达应用的时钟和数据恢复IC
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833604
P. Capofreddi, C.D. Baringer, J. Jensen, M. Rodwell, W. P. Posey, M. Yung, Y. Xie
{"title":"A clock and data recovery IC for communications and radar applications","authors":"P. Capofreddi, C.D. Baringer, J. Jensen, M. Rodwell, W. P. Posey, M. Yung, Y. Xie","doi":"10.1109/MMICA.1999.833604","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833604","url":null,"abstract":"A clock and data recovery (CDR) circuit for communications and radar applications was designed and fabricated in a 0.8 /spl mu/m, 27 GHz f/sub T/ bipolar process. Experimental measurements demonstrate that the circuit achieves a data rate of 4 Gbit/s with a bit error rate less than 10/sup -7/. The circuit includes two phase-locked loops for clock recovery, a delay-locked loop for synchronizing multiple channels with different path delays, and a 1:16 tree-type demultiplexer. In operation, the circuit consumes 3 W from a single 3.3 V power supply.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132136674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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