Design of domino CMOS cells under delay constraint

Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI:10.1109/MMICA.1999.833610

A. Zamudio, V. Champac, A. Sarmiento-Reyes

引用次数: 2

Abstract

Simple expressions to estimate the delay and power consumption of domino gates have been developed. Using these expressions design guidelines are established for domino cells under a specified delay. It has been found that there is a trade-off between the power consumption and noise margin for domino cells designed for a specified delay. A good correspondence exists between the theoretical and simulated results.

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延迟约束下的多米诺CMOS电池设计

给出了估计多米诺门延迟和功耗的简单表达式。利用这些表达式，建立了在特定延迟下的多米诺骨牌单元的设计准则。研究发现，在为特定延迟设计的多米诺骨牌细胞的功耗和噪声裕度之间存在权衡。理论计算结果与仿真结果吻合较好。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)

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