用于通信和雷达应用的时钟和数据恢复IC

Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI:10.1109/MMICA.1999.833604

P. Capofreddi, C.D. Baringer, J. Jensen, M. Rodwell, W. P. Posey, M. Yung, Y. Xie

{"title":"用于通信和雷达应用的时钟和数据恢复IC","authors":"P. Capofreddi, C.D. Baringer, J. Jensen, M. Rodwell, W. P. Posey, M. Yung, Y. Xie","doi":"10.1109/MMICA.1999.833604","DOIUrl":null,"url":null,"abstract":"A clock and data recovery (CDR) circuit for communications and radar applications was designed and fabricated in a 0.8 /spl mu/m, 27 GHz f/sub T/ bipolar process. Experimental measurements demonstrate that the circuit achieves a data rate of 4 Gbit/s with a bit error rate less than 10/sup -7/. The circuit includes two phase-locked loops for clock recovery, a delay-locked loop for synchronizing multiple channels with different path delays, and a 1:16 tree-type demultiplexer. In operation, the circuit consumes 3 W from a single 3.3 V power supply.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A clock and data recovery IC for communications and radar applications\",\"authors\":\"P. Capofreddi, C.D. Baringer, J. Jensen, M. Rodwell, W. P. Posey, M. Yung, Y. Xie\",\"doi\":\"10.1109/MMICA.1999.833604\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A clock and data recovery (CDR) circuit for communications and radar applications was designed and fabricated in a 0.8 /spl mu/m, 27 GHz f/sub T/ bipolar process. Experimental measurements demonstrate that the circuit achieves a data rate of 4 Gbit/s with a bit error rate less than 10/sup -7/. The circuit includes two phase-locked loops for clock recovery, a delay-locked loop for synchronizing multiple channels with different path delays, and a 1:16 tree-type demultiplexer. In operation, the circuit consumes 3 W from a single 3.3 V power supply.\",\"PeriodicalId\":221297,\"journal\":{\"name\":\"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-07-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MMICA.1999.833604\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MMICA.1999.833604","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

设计并制作了一种用于通信和雷达应用的时钟和数据恢复(CDR)电路，其工艺为0.8 /spl mu/m, 27 GHz f/sub / T双极工艺。实验测试表明，该电路的数据传输速率可达4gbit /s，误码率小于10/sup -7/。该电路包括用于时钟恢复的两个锁相环，用于同步具有不同路径延迟的多个通道的一个延迟锁相环，以及一个1:16树形解复用器。在工作中，该电路从单个3.3 V电源消耗3w。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A clock and data recovery IC for communications and radar applications

A clock and data recovery (CDR) circuit for communications and radar applications was designed and fabricated in a 0.8 /spl mu/m, 27 GHz f/sub T/ bipolar process. Experimental measurements demonstrate that the circuit achieves a data rate of 4 Gbit/s with a bit error rate less than 10/sup -7/. The circuit includes two phase-locked loops for clock recovery, a delay-locked loop for synchronizing multiple channels with different path delays, and a 1:16 tree-type demultiplexer. In operation, the circuit consumes 3 W from a single 3.3 V power supply.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)

自引率

0.00%

发文量