A clock and data recovery IC for communications and radar applications

Abstract

A clock and data recovery (CDR) circuit for communications and radar applications was designed and fabricated in a 0.8 /spl mu/m, 27 GHz f/sub T/ bipolar process. Experimental measurements demonstrate that the circuit achieves a data rate of 4 Gbit/s with a bit error rate less than 10/sup -7/. The circuit includes two phase-locked loops for clock recovery, a delay-locked loop for synchronizing multiple channels with different path delays, and a 1:16 tree-type demultiplexer. In operation, the circuit consumes 3 W from a single 3.3 V power supply.