Testing switched-current memory cells using DC stimuli

Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI:10.1109/MMICA.1999.833586

M. Renovell, F. Azais, J.-C. Bodin, Y. Bertrand

引用次数: 10

Abstract

The authors study the efficiency of a DC test for a memory cell, which is the elementary building block for switched-current circuits. Simulations are performed on two different cells. It is demonstrated that most of the hard faults are detected using one single input test current for the basic cascode memory cell, and two reverse-sign currents for the S/sup 2/I cascode memory cell. This study is also extended taking into account different values for the short and open resistance.

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使用直流刺激测试开关电流记忆单元

作者研究了存储单元的直流测试效率，存储单元是开关电流电路的基本组成部分。在两个不同的单元上进行了模拟。结果表明，使用基本级联存储器单元的单输入测试电流和S/sup 2/I级联存储器单元的两个反符号电流检测大多数硬故障。考虑到短路电阻和开路电阻的不同值，本研究也得到了扩展。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)

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