Adaptive analog timer for on-chip testing

Abstract

A practical approach for generating precise and slow analog ramps to be used for on-chip time-domain analog testing and for monotonicity and histogram test of ADCs is introduced. The calibration uses a discrete-time adaptive scheme. Two implementations of the approach are proposed; one is continuous-time and the second is discrete-time. Convergence criteria are defined. Results from a fabricated circuit in a low-cost 2 /spl mu/m technology are in agreement with theoretical results.