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2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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Current voltage characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET) 部分贫硅在铁电绝缘子场效应晶体管(pd - sofet)上的电流电压特性
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282048
Azzedin D. Es-Sakhi, M. Chowdhury
{"title":"Current voltage characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET)","authors":"Azzedin D. Es-Sakhi, M. Chowdhury","doi":"10.1109/MWSCAS.2015.7282048","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282048","url":null,"abstract":"This paper presents the current-voltage (I-V) characteristics of the recently proposed Silicon-on-Ferroelectric Insulator Field Effect Transistor (SOFFET). In this work we have concentrated on Partially Depleted (PD) structure. PD-SOFFET is based on the silicon-on-insulator (SOI) device technology and utilizes a negative capacitance that can be achieved by inserting a layer of ferroelectric insulator inside the bulk silicon substrate of the device. The negative capacitance (NC) effect can provide an internal signal boosting that leads to steeper subthreshold slope, which is the prime requirement for ultra-low-power circuit operation. Here we have analyzed the impacts of channel doping profile on the behavior of the proposed PD-SOFFET. The major focus of this paper is the investigation of the current-voltage (I-V) characteristics of the proposed device in both the subthreshold and the saturation regions.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"604 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116368412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Proposal of LED-based Peeping Prevention System 基于led防偷窥系统的设计方案
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282122
Kyosuke Kageyama, Kohei Sugiyama, T. Kumaki, T. Fujino
{"title":"Proposal of LED-based Peeping Prevention System","authors":"Kyosuke Kageyama, Kohei Sugiyama, T. Kumaki, T. Fujino","doi":"10.1109/MWSCAS.2015.7282122","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282122","url":null,"abstract":"Various crimes can be committed by using camera-embedded mobile device. In particular, peeping and digital shoplifting are increasing rapidly. No direct countermeasures have been taken against these crimes, so potential victims have to prevent these crimes themselves. To overcome these problems, this paper proposes a crime prevention method called Peeping Prevention System (PPS) that uses an LED visible light beacon to prevent a camera from taking photos. PPS generates several beacons by changing the brightness intensity of an LED light bulb. After the camera receives this beacon, the proposed system forces the camera function to stop automatically. In this paper, we construct a prototype of PPS to demonstrate the system. Since the transmitter is to transmit light in public places, this transmitter must not transmit a beacon that discomforts people's eyes. The receiver is used in a smartphone camera and has programs to control the camera and receive the beacon. We confirm regular LED lighting can stop the camera function. Then, we check the reception accuracy of the camera and test the discomfort caused by the beacon. The camera is stopped within 25 seconds regardless of distance and angle between the LED lighting and the camera. Finally, a logarithmic wave is found to be a more comfortable beacon than a linear wave.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116813436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS-MEMS novel resonator for filter tuning 用于滤波器调谐的CMOS-MEMS新型谐振器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282017
H. Goktas, M. Zaghloul
{"title":"CMOS-MEMS novel resonator for filter tuning","authors":"H. Goktas, M. Zaghloul","doi":"10.1109/MWSCAS.2015.7282017","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282017","url":null,"abstract":"Novel MEMS resonators are presented in this work, and were designed in CMOS process. The devices were fabricated and tested. The work shows the combined CMOS and MEMS process. The resonators are designed in Fixed -Fixed beam structure. Applications are low power temperature tuning filters, and temperature sensors.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116653532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications 具有180°混合片上耦合器的CMOS功率放大器，用于4G应用
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282076
Mahima Arrawatia, M. Baghini, G. Kumar
{"title":"A CMOS power amplifier with 180° hybrid on-chip coupler for 4G applications","authors":"Mahima Arrawatia, M. Baghini, G. Kumar","doi":"10.1109/MWSCAS.2015.7282076","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282076","url":null,"abstract":"This paper presents a CMOS Class AB power amplifier with an on-chip 180° hybrid coupler for 4G applications. Two-stage power amplifier architecture with a combination of low voltage core transistor and high voltage I/O transistors, is designed to achieve the power gain in the 180nm standard CMOS technology. The driver stage has a power gain of 18.5dB and linear output power of 12.9dBm. The power stage has a gain of 13.7dB and P1dB of 24.4dBm. The paper also presents an on-chip 180° hybrid coupler, designed in the same technology, for combining the power generated from individual power amplifiers. The measured results of the coupler show an isolation better than -30dB, S11 better than -20dB and, S21 and S31 equal to -5.4dB, at 2.35GHz. The complete differential power amplifier using the on-chip coupler gives P1dB of 26.4dBm and saturated output power of 27.4dBm. As compared to all the reported on-chip couplers configurations, use of 180° hybrid coupler leads to better load insensitivity as well as improved linearity due to the second harmonic cancellation.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115813030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-power hybrid ADC architecture for high-speed medium-resolution applications 适用于高速中分辨率应用的低功耗混合ADC架构
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282032
Seyed Alireza Zahrai, M. Onabajo
{"title":"A low-power hybrid ADC architecture for high-speed medium-resolution applications","authors":"Seyed Alireza Zahrai, M. Onabajo","doi":"10.1109/MWSCAS.2015.7282032","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282032","url":null,"abstract":"A low-power hybrid analog-to-digital converter (ADC) architecture for high-speed medium-resolution applications is introduced. The architecture is a subranging time-interleaved ADC. In the first stage, a fast flash ADC resolves the three most significant bits. The remaining bits are generated by four time-interleaved low-power successive approximation register (SAR) ADCs, leading to 8-bit 1GS/s operation overall. A combined sample-and-hold and capacitive digital-to-analog converter (SHDAC) circuit is proposed to perform front-end sampling and to shift the sampled voltage to the optimal operating region of the second stage. A buffer stage suppresses the loading effects and kickback noise of the SAR ADC on the SHDAC in each channel. Each SAR ADC is implemented with a comparator-based asynchronous binary-search (CABS) architecture. A switching scheme in the voltage buffer stage relaxes the amplifier specification requirements, leading to significant power reduction. The hybrid ADC was designed and simulated with a mix of behavioral models and transistor-level circuit designs in 130nm CMOS technology. It has a signal-to-noise-and-distortion ratio (SNDR) of 47.5dB with an input signal close to the Nyquist frequency. The estimated power consumption is 17mW from a 1.2V supply.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114240741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Optimization of antenna beam pattern in ad hoc networks for optimal global performance 面向全局性能优化的自组网天线波束方向优化
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282046
V. Ramakrishnaiah, R. Kubichek, S. Muknahallipatna
{"title":"Optimization of antenna beam pattern in ad hoc networks for optimal global performance","authors":"V. Ramakrishnaiah, R. Kubichek, S. Muknahallipatna","doi":"10.1109/MWSCAS.2015.7282046","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282046","url":null,"abstract":"Directional antennas shape transmission patterns to provide greater coverage distance and reduced coverage angle. When used in an ad-hoc network, this reduces interference among transmitting nodes and thereby increases throughput. A problem that has not been addressed is how to compute individual beam patterns that maximize some measure of global network performance. Historically, the focus has been on finding node antenna patterns that give locally optimal performance. In this paper we investigate a low hardware complexity beamforming approach aimed at improving global performance. Given a multi-hop route from source to destination, beam patterns are shaped to maximize average signal-to-noise ratio across all nodes on the route, which reduces bit-error rates and extends battery and network lifetime. By using phase-only weights, hardware costs are minimized.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"95 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126191216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A wide range and high conversion gain power detector for frequency shift sensing applications 宽范围和高转换增益功率检测器，用于频移传感应用
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282030
Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang
{"title":"A wide range and high conversion gain power detector for frequency shift sensing applications","authors":"Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang","doi":"10.1109/MWSCAS.2015.7282030","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282030","url":null,"abstract":"This paper demonstrates a high frequency power detector with high conversion gain for frequency-shift sensing applications used in biosensing systems. The proposed design comprises an amplitude-to-voltage convertor (AVC), a peak detector, and a bandgap. To increase the operating frequency range, AVC utilizes half of an RMS power detector to attain the power measure of an input signal. Since the input power is converted to a DC voltage by AVC, the peak detector will secure the resonant frequency when AVC generates the highest voltage. The proposed power detector circuit is realized on silicon using a 60 V 0.25 μm CMOS technology. Measurement results show that the proposed circuit is able to detect input frequency from 500 Hz to 2.5 GHz. The conversion gain of AVC is 166.6 mV/dB, and the power consumption is 5.25 mW given a 5 V power supply voltage.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128197476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Delta DICE: A Double Node Upset resilient latch Delta DICE:双节点翻转弹性闩锁
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282145
Nikolaos Eftaxiopoulos-Sarris, N. Axelos, Georgios Zervakis, Kostas Tsoumanis, K. Pekmestzi
{"title":"Delta DICE: A Double Node Upset resilient latch","authors":"Nikolaos Eftaxiopoulos-Sarris, N. Axelos, Georgios Zervakis, Kostas Tsoumanis, K. Pekmestzi","doi":"10.1109/MWSCAS.2015.7282145","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282145","url":null,"abstract":"In this paper we propose the novel Delta DICE latch that is tolerant to SNUs (Single Node Upsets) and DNUs (Double Node Upsets). The latch comprises three DICE cells in a delta interconnection topology, providing enough redundant nodes to guarantee resilience to conventional SNUs, as well as DNUs due to charge sharing. Simulation results demonstrated that in terms of power dissipation and propagation delay, the Delta DICE latch outperforms BISER-based latches that are SNU or DNU tolerant and provides DNU resilience at a small energy×delay penalty compared to other SNU tolerant cells.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125209572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Low-power, serial interface for power-constrained devices 低功耗，串行接口，用于功率受限的设备
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282105
B. Degnan, J. Hasler
{"title":"Low-power, serial interface for power-constrained devices","authors":"B. Degnan, J. Hasler","doi":"10.1109/MWSCAS.2015.7282105","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282105","url":null,"abstract":"Low-power digital interfaces are a crucial component of reconfigurable systems. We have designed a SPI-compatible, four-wire interface and state machine for use in dynamically scaled voltage systems. The interface features an activity enable signal and latch enable signal on every eighth-bit in order to minimize the total switching power consumed by the interface. The interface also allows for addressing for disparate systems across the IC to share a common bus without contention.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121878027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A netlist implementation of the Newton fixed-point homotopy method for MOS transistor circuits MOS晶体管电路牛顿不动点同伦法的网表实现
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282088
Dan Niu, Y. Inoue, Zhou Jin, Xiao Wu
{"title":"A netlist implementation of the Newton fixed-point homotopy method for MOS transistor circuits","authors":"Dan Niu, Y. Inoue, Zhou Jin, Xiao Wu","doi":"10.1109/MWSCAS.2015.7282088","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282088","url":null,"abstract":"Recently, an efficient and globally convergent Newton fixed-point homotopy method (NFPH) for MOS transistor circuits has been proposed to find dc solutions of nonlinear circuits. However, the programming of sophisticated homotopy methods is often difficult for non-experts. In this paper, an effective netlist implementation method for the MOS NFPH method is proposed and it can implement the MOS NFPH method from a good initial solution with various efficient techniques and without programming. Moreover, the “probe” algorithm in BJT circuits is extended to MOS NFPH method for achieving high efficiency and the existence theorem is given.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121538002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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