2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

筛选
英文 中文
An active rectifier with optimal flip timing for the internal capacitor for piezoelectric vibration energy harvesting 一种用于压电振动能量收集的内部电容器的最佳翻转时间有源整流器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282121
Liao Wu, D. Ha, Jishun Kuang, Xuan-Dien Do, Sang-Gug Lee
{"title":"An active rectifier with optimal flip timing for the internal capacitor for piezoelectric vibration energy harvesting","authors":"Liao Wu, D. Ha, Jishun Kuang, Xuan-Dien Do, Sang-Gug Lee","doi":"10.1109/MWSCAS.2015.7282121","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282121","url":null,"abstract":"This paper presents an active rectifier, which aims to extract maximum power from piezoelectric generators for vibration energy harvesting. A nonlinear impedance matching scheme called Synchronized Switch Harvesting on Inductor (SSHI) is highly effective [1]. However, control of the internal capacitor flip timing is complicated to result in a complex controller or suboptimal flip timing. We proposed an active rectifier based on the series SSHI configuration [2]. It ensures an optimal capacitor flip timing, yet the controller is simple to dissipate low power and hence achieve high efficiency. One potential problem of the series SSHI scheme is a non-robust operation due to parasitics and a variety of characteristics of the piezoelectric generators. We present an improved rectifier, which address the problem. The improved rectifier is designed in 0.25 μm BiCMOS process. Post-layout simulation results indicate robust operation and high efficiency of 93%, which is comparable to the original design in [2] and far higher than other existing SSHI rectifiers reported.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"415 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131769387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy-efficient NoC with variable channel width 具有可变信道宽度的节能NoC
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282188
Cheng Li, P. Ampadu
{"title":"Energy-efficient NoC with variable channel width","authors":"Cheng Li, P. Ampadu","doi":"10.1109/MWSCAS.2015.7282188","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282188","url":null,"abstract":"Although Network-on-Chip (NoC) has become a popular solution for multicore system, its power consumption is still a concern for power-constrained design. We propose a NoC with variable channel width to achieve better energy-efficiency for NoC traffics in real systems. Based on the observation that short control messages account for a significant portion of NoC traffic, we use wide channel (128-bit) to transmit long data messages while dynamically split it into 2 narrower channels (64-bit) for short messages and shut down the unused channel to save energy. With workloads from PARSEC 2.1 benchmark suits, our proposed approach reduces NoC power consumption by up to 25%. More power saving can be achieved as injection rate increases under synthetic traffics. Besides, our method has no impact on performance and its induced area overhead is negligible.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114602855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
DAC mismatch shaping for quadrature sigma-delta data converters 正交σ - δ数据转换器的DAC失配整形
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282149
S. Kundu, Subhanshu Gupta, D. Allstot, J. Paramesh
{"title":"DAC mismatch shaping for quadrature sigma-delta data converters","authors":"S. Kundu, Subhanshu Gupta, D. Allstot, J. Paramesh","doi":"10.1109/MWSCAS.2015.7282149","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282149","url":null,"abstract":"An intuitive yet mathematically rigorous procedure for arriving at a DAC element rotation algorithm (ERA) from a given general mismatch transfer function (MTF) is presented for sigma-delta data converters. The approach is validated by deriving low-pass and high-pass ERAs from the corresponding MTFs. Using the proposed approach the ERA for a quadrature sigma-delta ADC is then derived from a quadrature MTF. Simulations show that the new low-complexity quadrature ERA performs better than previously proposed quadrature ERAs of similar complexity. A gain calibration technique is further proposed that works in conjunction to the quadrature ERA to alleviate the image-folding due to mismatches between the quadrature DAC elements.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114464587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Derivative-free active-RC elliptic filter using cascade of biquads in 28 nm CMOS 28nm CMOS双极级联无导数有源rc椭圆滤波器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282083
S. Thirunakkarasu, Frank W. Singor, Jie Fang, S. Ganesan, Jose Fabian Silva-Rivas, K. Deenadayalan, B. K. Thandri, Chaoming Zhang, Xuefeng Yu, Nand Jha, Ardie G. Venes
{"title":"Derivative-free active-RC elliptic filter using cascade of biquads in 28 nm CMOS","authors":"S. Thirunakkarasu, Frank W. Singor, Jie Fang, S. Ganesan, Jose Fabian Silva-Rivas, K. Deenadayalan, B. K. Thandri, Chaoming Zhang, Xuefeng Yu, Nand Jha, Ardie G. Venes","doi":"10.1109/MWSCAS.2015.7282083","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282083","url":null,"abstract":"A highly linear, 3rd order, active-RC low-pass elliptic filter with Variable Gain Amplifier (VGA) is presented. The new derivative-free biquad topology for an elliptic filter could be easily extended to a higher order filter using a cascade of biquads and it will have a zero capacitive spread when used along with a VGA. It is introduced to minimize the power consumption of an active-RC filter in a radio receiver. The combination of a filter+VGA provides a ripple of just 0.4 dB through 35 MHz pass-band and sharply attenuates out of band carriers by placing a zero at 50 MHz. A Filter+VGA together achieves an IIP3 of 29.91 dBm and integrated input referred noise of 44.96 μVrms consuming 54 mW. The proposed architecture is simulated using 28 nm CMOS technology and verified through extensive spectre simulations.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114596294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Generation and distribution of microwave signals by using optoelectronic oscillators 利用光电振荡器进行微波信号的产生与分布
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282073
A. G. Correa-Mena, P. Hernández-Nava, I. Zaldívar-Huerta, Amanda D. Salas-Caridad, J. Rodríguez-Asomoza, A. García-Juárez, M. Won-Lee
{"title":"Generation and distribution of microwave signals by using optoelectronic oscillators","authors":"A. G. Correa-Mena, P. Hernández-Nava, I. Zaldívar-Huerta, Amanda D. Salas-Caridad, J. Rodríguez-Asomoza, A. García-Juárez, M. Won-Lee","doi":"10.1109/MWSCAS.2015.7282073","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282073","url":null,"abstract":"We experimentally demonstrate the generation and distribution of a microwave signal by using an optoelectronic oscillator. This system can be easily configured to generate microwave signals tuned over a very broad frequency range by selecting an appropriate optical delay. Experimental results show a good signal-to-noise-ratio at 4.1GHz.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125032472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigating power characteristics of memristor-based logic gates and their applications in a security primitive 研究基于忆阻器的逻辑门的功率特性及其在安全原语中的应用
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282128
Jaya Dofe, Jonathan Frey, P. Nsengiyumva, Qiaoyan Yu
{"title":"Investigating power characteristics of memristor-based logic gates and their applications in a security primitive","authors":"Jaya Dofe, Jonathan Frey, P. Nsengiyumva, Qiaoyan Yu","doi":"10.1109/MWSCAS.2015.7282128","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282128","url":null,"abstract":"The fourth fundamental circuit element, memristor, attracts increasing attention because of its memory characteristic. The special memory behavior of the memristor has been exploited to design control systems, memory arrays, logic gate, and security primitives in previous work. However, the power characteristics of the memristor have not been widely studied yet. In this work, we used a memristor model that is suitable for circuit simulation to investigate the power characteristics of the memristor itself and memristor-based logic gates. Our simulation results indicate that memristor has different power characteristic compared with CMOS devices. The peak power of memristor-based gates does not monotonically increases with input voltage amplitude; instead, the combination of input period length and voltage amplitude determines the occurrence of power peak. The reason is that the power consumption of memristors depends on the effective memristor width, which is controlled by the input. We further examine the feasibility of utilizing memristors to implement a new block cipher, SIMON. Our studies show that the unique power characteristic of memristor based SIMON may add extra challenges for extraction of the secret key from the cipher as it introduces 94% power deviation while power sampling.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127156541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
0.25–4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme 0.25-4 ns 185 MS/s 4位脉冲收缩时间到数字转换器在130纳米CMOS使用两步转换方案
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282113
Young Jun Park, F. Yuan
{"title":"0.25–4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme","authors":"Young Jun Park, F. Yuan","doi":"10.1109/MWSCAS.2015.7282113","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282113","url":null,"abstract":"An area and power efficient pulse-shrinking delay-line time-to-digital converter (TDC) using a 2-step conversion scheme is presented. The proposed TDC quantizes time variables using a coarse pulse-shrinking TDC with a large per-stage time shrinkage and a fine pulse-shrinking TDC with a small per-stage time shrinkage. It offers low power and silicon consumption, and good linearity without sacrificing resolution. The proposed TDC has been designed in an IBM 130 nm 1.2 V CMOS technology. The input range of the TDC is 4 ns, conversion rate 185 MS/s, resolution 250 ps, INL of 1 LSB, and figure-of-merit 0.163 pJ/conv.step.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131991635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A single-ended chopper-stabilized ISFET amplifier for continuous pH measurement applications 用于连续pH测量应用的单端斩波稳定ISFET放大器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282183
M. Asgari, Kye-Shin Lee
{"title":"A single-ended chopper-stabilized ISFET amplifier for continuous pH measurement applications","authors":"M. Asgari, Kye-Shin Lee","doi":"10.1109/MWSCAS.2015.7282183","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282183","url":null,"abstract":"This paper introduces a novel low-power Ion-Sensitive Field Effect Transistor (ISFET) readout configuration compatible with standard CMOS technology that utilizes chopping technique to reduce the 1/f noise and the offset of the readout circuitry. In addition, the proposed scheme tackles the well-known non-idealities of the ISFET such as the trapped charge and the long-term drift by using a resetting switch, while suppressing the imperfections of the resetting switch with the proposed chopping amplifier. The readout circuitry can be applied to both continuous time or difference pH measurements. Simulation results using standard 0.35μm CMOS technology shows 20 dB reduction in the output noise while the ISFET readout circuit including the integrator consumes 950nW.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128845999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Delta Sigma based Finite Impulse Response Filter for EEG Signal Processing 基于δ σ的有限脉冲响应滤波器在脑电信号处理中的应用
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282192
Yifei Liu, Wei Tang
{"title":"A Delta Sigma based Finite Impulse Response Filter for EEG Signal Processing","authors":"Yifei Liu, Wei Tang","doi":"10.1109/MWSCAS.2015.7282192","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282192","url":null,"abstract":"This paper presents the design of a Finite Impulse Response Filter based on Delta Sigma Signal Processing. Both input and output of the proposed circuit are encoded as second-order Delta Sigma bit-streams. The design is realized using a Delta Sigma adder based on an input counter. The Delta Sigma adder can also be used as a coefficient multiplier. Using the proposed Delta Sigma adder and coefficient multiplier, an Finite Impulse Response filter is designed for Electroencephalogram signal processing. Simulation and synthesis results are shown based on IBM 180nm CMOS technology. The proposed design achieves a Θ(N) complexity with N inputs and can work with higher-order Delta Sigma bit-streams.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129107955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Efficient architecture and implementation for NTRUEncrypt system NTRUEncrypt系统的高效架构与实现
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282143
Bingxin Liu, Huapeng Wu
{"title":"Efficient architecture and implementation for NTRUEncrypt system","authors":"Bingxin Liu, Huapeng Wu","doi":"10.1109/MWSCAS.2015.7282143","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282143","url":null,"abstract":"NTRU has gained much attention recently because it is relatively efficient for practical implementation among the post-quantum public key cryptosystems. In this paper, an efficient hardware architecture and FPGA implementation of NTRUEncrypt is proposed. The new architecture takes advantage of linear feedback shift register (LFSR) structure for its compact circuitry and high speed. A novel design of the modular arithmetic unit is proposed to reduce the critical path delay. The FPGA implementation results have shown that the proposed design outperforms all the existing works in terms of area-delay product.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116003520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信