Rongyang Liu, J. Delgado-Frías, Doug Boyce, R. Khanna
{"title":"UEFI USB bus initialization verification using Colored Petri Net","authors":"Rongyang Liu, J. Delgado-Frías, Doug Boyce, R. Khanna","doi":"10.1109/MWSCAS.2015.7282158","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282158","url":null,"abstract":"In this paper we present a novel scheme to perform firmware verification using a graphical Colored Petri Net (CPN). CPNs provide modeling features for concurrency, communication and synchronization as well as hierarchical abstraction and timing analysis. These features are used to perform firmware validation of the UEFI USB bus initialization. The CPN representation provides better visualization support to streamline the validation process. A Beagle Board is used to show the potential of the proposed firmware validation scheme.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121342377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MDLL/PLL dual-path clock generator","authors":"H. Sun, U. Moon","doi":"10.1109/MWSCAS.2015.7282044","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282044","url":null,"abstract":"This paper proposes an MDLL/PLL dual-path clock generator. By splitting a single delay line into two halves, both a voltage controlled delay-line (VCDL) and a voltage controlled oscillator (VCO) can be implemented. Since both the integral and proportional paths can be configured in this way, stabilizing zero is inherently obtained. Elimination of the zero-insertion resistor in a loop-filter mitigates several drawbacks of a conventional charge-pump (CP) PLL. The comparison between the conventional CP-PLL and the proposed architecture reveals significant power and chip area savings with better jitter performance.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127480683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-power two-stage harmonic rejection quadrature mixer employing bias-current reuse","authors":"Wei-Gi Ho, Travis Forbes, R. Gharpurey","doi":"10.1109/MWSCAS.2015.7282134","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282134","url":null,"abstract":"A bias-sharing two-stage harmonic rejection mixer that provides quadrature baseband outputs is demonstrated. The devices that bias the RF transconductors in a one-stage harmonic-rejection downconverter are configured to provide a second-stage of harmonic rejection for reducing the impact of gain coefficient errors, without requiring additional bias current. Clock retiming is used to desensitize the design to clock phase errors. The design is implemented in a 130nm CMOS process, and demonstrates a gain of 35.8 dB, an in-band output 1dB compression of -6 dBVp, a DSB NF of 11.5 dB, and an analog power dissipation of 14 mW from a 1.2 V supply. Harmonic rejection in excess of 60 dB is measured without calibration. Operation using a clock frequency in the range from 800 MHz to 2 GHz is verified. Mechanisms relating to bias-sharing that can potentially degrade performance including flicker noise and even-order harmonic response are identified. Circuit techniques for mitigating these issues that exploit orthogonal phasing of RF and baseband signals are described.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123322348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real-time VLSI architecture for palm rejection using Wronskian Determinant","authors":"Abu M. Baker, Yingtao Jiang","doi":"10.1109/MWSCAS.2015.7282154","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282154","url":null,"abstract":"Several Human Interface Technology applications require reliable palm rejection. Palm rejection in upcoming touch or Pad technology has a need of hardware implementation with requirements of low power and small area. This paper introduces a hardware implementation of a real-time palm rejection based on Wronskian Determinant. This detection algorithm offers regularity, low complexity and accuracy as well as robustness against global illumination changes. The proposed architecture is able to process incoming frames on-the-fly, therefore requiring a small amount of memory. The maximum frame rate is 15 fps, however the implementation is flexible enough to allow analysis of less frames if required. Processing unit consist of a basic processing element implemented in pipeline fashion and adder tree to produce final results. The architecture was implemented using a XCV800 FPGA. The power consumption of the whole system is 93 mW.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128382957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1.1–8.2 GHz tuning range In-phase and Quadrature output DCO design in 90 nm CMOS technology","authors":"E. R. Suraparaju, P. Arja, S. Ren","doi":"10.1109/MWSCAS.2015.7282171","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282171","url":null,"abstract":"This paper presents a high-frequency wide tuning range Digital Control Oscillator (DCO) with In-phase and Quadrature outputs designed using a 90nm CMOS process with 1.2 V power supply. The proposed design operates in the frequency range of 1.1-8.2GHz. The designed ring oscillator with digital control inputs attains high oscillation frequencies by applying negative delay inputs to the transistors in parallel to the conventional static CMOS inverter. The stage delay of the ring oscillator with the proposed design is less than the conventional static CMOS inverter and the skewed delay inverter cell. At 2.02GHz oscillation frequency, the measured phase noise is -90.43dBc/Hz at an offset of 1 MHz and -117.64dBc/Hz at an offset of 10MHz.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wenchao Lu, Wenbo Chen, Prem Thapaliya, Ryan O' Dell, R. Jha
{"title":"Switching characteristics of MgO based self-compliant ReRAM devices","authors":"Wenchao Lu, Wenbo Chen, Prem Thapaliya, Ryan O' Dell, R. Jha","doi":"10.1109/MWSCAS.2015.7282090","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282090","url":null,"abstract":"We report the impact of titanium (Ti) and TiOx interfacial layers on switching characteristics of MgO based Resistive Random Access Memory (ReRAM) devices. The devices with Ti/MgO and Ti/TiOx/MgO bi-layer structures demonstrated bipolar resistive switching characteristics with self-compliance behavior and low set/reset voltages. Much lower self-compliance current was observed for Ti/TiOx/MgO devices compared to Ti/MgO devices. The mechanism behind this observation was explained based on oxygen ions and oxygen vacancies transport between TiOx and MgO layers.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129292512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System parameter analysis on devices with Bi-stable characteristics","authors":"Hossein Sarafraz, M. Sayeh","doi":"10.1109/MWSCAS.2015.7282016","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282016","url":null,"abstract":"In this paper an investigation has been done on the parameters of a hysteretic bi-stable device. From a design point of view it is important to know the regions where this bi-stability occurs and is fully functional with respect to its subsystem parameters. Specifically a known structure of photonic Schmitt trigger that consist of two inverting amplifiers, each characterized by -m (slope), A (y-intercept) and B (constant base) parameters is considered. In addition to a complete mathematical analysis of the system, this paper also describes how m, A and B can be properly chosen in order to satisfy certain system conditions. For a special case of B = 0, it is found and shown that we must have (m1 <; 1 & m2 > 1) as absolute conditions for the bi-stable device (m > 0 is assumed). Also system conditions add more restrictions to these absolute conditions as discussed in the last section of this paper.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129791105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Asynchronous communication for wireless sensors using ultra wideband impulse radio","authors":"Qisong Hu, Chen Yi, J. Kliewer, Wei Tang","doi":"10.1109/MWSCAS.2015.7282170","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282170","url":null,"abstract":"This paper addresses simulations and design of an asynchronous integrated ultra wideband impulse radio transmitter and receiver suitable for low-power miniaturized wireless sensors. This paper first presents software simulations for asynchronous transmission over noisy channels using FSK-OOK modulation, which demonstrates that the proposed architecture is capable to communicate reliably at moderate signal-to-noise ratios and that the main errors are due to deletions of received noisy transmit pulses. Then, we address a hardware chip implementation of the integrated UWB transmitter and receiver, which is fabricated using an IBM 0.18μm CMOS process. This implementation provides a low peak power consumption, i.e., 10.8 mW for the transmitter and 5.4 mW for the receiver, respectively. The measured maximum baseband data rate of the proposed radio is 2.3 Mb/s.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Overload analysis of continuous time sigma delta modulators","authors":"Kyung Kang, P. Stubberud","doi":"10.1109/MWSCAS.2015.7282163","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282163","url":null,"abstract":"When a continuous time sigma delta modulator (CT ΣΔM) is overloaded, its output signal to quantization noise ratio (SQNR) decreases when the ΣΔM's input power is increased over a certain value. In this paper, the range of quantizer gains that cause a CT ΣΔM to overload is determined, and this range of values is used to determine the maximum input signal power that prevents overload. To validate the predicted maximum input power that prevents overload, 2nd through 5th order CT ΣΔMs are simulated.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121302451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Concurrent dual-band LNA for automotive application","authors":"M. Gamal, M. El-Nozahi, H. El-Hennawy","doi":"10.1109/MWSCAS.2015.7282092","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282092","url":null,"abstract":"This paper presents a concurrent CMOS dual-band LNA (DB-LNA) targeting the FCC automotive short and long range radar bands located at 25.5 GHz and 76.5 GHz, respectively. The DB-LNA utilizes a second order dual-band matching network to achieve a 7 GHz bandwidth in the input matching network at 25.5 GHz. Mathematical formulas assist in determining the matching network and output load components values are presented. The DB-LNA is designed using 65nm CMOS technology and occupies an area of 0.166 mm2. The DB-LNA achieves a voltage gain of 16 dB and 10 dB and a noise figure of 3.5 dB and 8.2 dB at 25.5 GHz and 76.5 GHz, respectively, with a power consumption of 48 mW from a 1.2 V supply.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130685347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}