2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献_第10页

Design and implementation of an embedded system for monitoring at-home solitary Alzheimer's patients 一种嵌入式系统的设计与实现，用于监测居家独居阿尔茨海默病患者

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282201

R. P. O'Brien, S. Katkoori, M. Rowe

引用次数: 5

Scaled IIR filter based on stochastic computation 基于随机计算的缩放IIR滤波器

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282118

N. Onizawa, S. Koshita, T. Hanyu

引用次数: 8

Physical design and implementation of POWER8™ (P8) server class processor POWER8™(P8)服务器类处理器的物理设计和实现

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282013

Mozammel Hossain, E. Fluhr, A. Hall, V. Agarwal

{"title":"Physical design and implementation of POWER8™ (P8) server class processor","authors":"Mozammel Hossain, E. Fluhr, A. Hall, V. Agarwal","doi":"10.1109/MWSCAS.2015.7282013","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282013","url":null,"abstract":"POWER8™ (P8) processor is a 12-core, 649mm2, 4.2B transistor chip fabricated in IBM's 22nm SOI technology with 2.5× socket performance improvement over its 32nm predecessor, POWER7+, driven by big data application and power efficient computing. Highly distributed chip voltage regulator achieves a peak power efficiency of 90.5%. Resonant clock design is used in 13 clock meshes to achieve about 4% power savings for the chip. This chip is built with three thin-oxide transistor Vt for power/performance benefit and one thick-oxide transistor to enable high-voltage circuits. In order to achieve desired performance within the power envelop, P8 is built with 7 input voltages and 15-layers of metals along with the use of pulsed-clock latches. The P8 has 15823 total pads: 5982 power, 7742 ground and 2099 signal. The power/performance complexity, size of the die, along with high operating frequency presented significant challenges to complete the design on an aggressive schedule. Some of the design methodology and implementation innovations in P8 have been presented in this paper, with an emphasis on macro design topologies (custom, array and synthesis), timing methodology, as well as the electrical characterizations performed in the chip bring-up lab.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126876957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A battery-less power management circuit for RF energy harvesting with input voltage regulation and synchronous rectification 一种用于射频能量收集的无电池电源管理电路，具有输入电压调节和同步整流

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282124

Gaurav Saini, Mahima Arrawatia, S. Sarkar, M. Baghini

{"title":"A battery-less power management circuit for RF energy harvesting with input voltage regulation and synchronous rectification","authors":"Gaurav Saini, Mahima Arrawatia, S. Sarkar, M. Baghini","doi":"10.1109/MWSCAS.2015.7282124","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282124","url":null,"abstract":"This paper presents a battery-less power management circuit for RF energy harvesting applications. In general rectenna (antenna and rectifier) exhibits the maximum efficiency for a particular range of load resistance at different values of RF power received by the antenna. To track maximum power transfer and reduce the power overhead of the various modules an efficient and simple scheme is presented in this paper to maintain effective input resistance of the boost converter equal to the effective output resistance of the rectenna. Maximum power point tracking (MPPT) is achieved at the input of boost converter and synchronous rectification technique is also used to stop the loss of energy from output capacitor of the boost converter. It is shown that MPPT as a function of effective output resistance of the rectenna can be maintained for a range of input power without changing the emulated resistance at the input of the boost converter. The entire circuit is designed, optimized and simulated in 180nm mixed-mode CMOS technology. Post layout simulation results are presented for -10dBm input power at 950MHz received by the antenna. Output voltage of 1V is generated across a load resistance of 76 kΩ with achieved boost converter efficiency of 80%.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126951457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency 中心频率精确可调的离散电荷域复带通滤波器分析

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282168

Yang Xu, H. Sun, U. Moon

引用次数: 0

High-throughput hardware implementation for motion estimation in HEVC encoder HEVC编码器中运动估计的高吞吐量硬件实现

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282040

A. Medhat, A. Shalaby, M. Sayed

引用次数: 17

A high precision and high speed voltage-mode loser/winner-take-all circuit 高精度、高速电压模式输者/赢者通吃电路

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282174

Punith R. Surkanti, Venu Siripurapu, P. Furth

引用次数: 4

FPGA design space exploration of IDEA cryptography IP core FPGA设计空间对IDEA加密IP核的探索

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282150

Dinesh Varma Penumetcha, Jiafeng Xie, S. Ren

引用次数: 4

A simple ramp generator with level spreading for SEIR based ADC BIST circuit 用于基于SEIR的ADC BIST电路的电平扩展的简单斜坡发生器

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282196

Hao Meng, Degang Chen

{"title":"A simple ramp generator with level spreading for SEIR based ADC BIST circuit","authors":"Hao Meng, Degang Chen","doi":"10.1109/MWSCAS.2015.7282196","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282196","url":null,"abstract":"In ADC BIST testing circuit, ramp signal is the most widely used stimulus because of its simple structure and ease of control. In addition, with SEIR algorithm, the linearity requirement of the ramp signal is highly relaxed. But for high resolution ADC BIST testing, the ramp signal must be repetitive for acquiring valid data because a single ramp will cost large area, which is not acceptable for BIST solution. However, the repetitive ramp signals that is synchronized by on chip clock will cause collected data to be useless, because voltage levels sampled on every ramp are the same. For accomplishing different sampling voltages on each ramp signal, a method of introducing level spreading to every ramp signal is proposed in this paper. An 8-bit non-linear DAC as level-spreading generator is designed to provide the number of voltage levels required. The proposed control circuit for BIST consists of an 8-bit counter and end-detector without decoders. Simulation results show that the proposed method works well for linearity test based on SEIR algorithm, while the non-linearity of level spreading DAC barely impacts test results.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125347520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Process variation immunity of alternative 16nm HK/MG-based FPGA logic blocks 可选的16nm HK/ mg FPGA逻辑块的工艺变异抗扰性

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282172

Ahmad Alzahrani, R. Demara

引用次数: 17