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2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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Inductorless bandwidth extension using local positive feedback in inverter-based TIAs 基于逆变器的TIAs中使用局部正反馈的无电感带宽扩展
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282179
Weihao Ni, Marc-Alexandre Chan, G. Cowan
{"title":"Inductorless bandwidth extension using local positive feedback in inverter-based TIAs","authors":"Weihao Ni, Marc-Alexandre Chan, G. Cowan","doi":"10.1109/MWSCAS.2015.7282179","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282179","url":null,"abstract":"This paper investigates an inductorless technique for bandwidth extension which uses local positive feedback in an optical receiver front-end based on an inverter-based transimpedance amplifier and Cherry-Hooper post-amplifiers. Small feedback inverters create negative resistance that boosts the output resistance of inverter-based amplifiers. Compared to a reference design having a TIA and a three-stage post-amplifier, the addition of equal local positive feedback, while keeping the gain unchanged at 85.8 dB, increased the bandwidth from 12.4 GHz to 18.3 GHz and the vertical eye opening by 8% at 26 Gb/s. The noise performance degraded from 9.67 pA/√Hz to 10.66 pA/√Hz, while power consumption increases minimally. Unequal positive feedback on each post-amplifier, while keeping gain and bandwidth unchanged, further improved performance. Guidelines for sizing the feedback inverters are given.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132528297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Energy-efficient reconfigurable computing using Spintronic memory 利用自旋电子存储器的节能可重构计算
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282213
Robert Karam, Kai Yang, S. Bhunia
{"title":"Energy-efficient reconfigurable computing using Spintronic memory","authors":"Robert Karam, Kai Yang, S. Bhunia","doi":"10.1109/MWSCAS.2015.7282213","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282213","url":null,"abstract":"Reconfigurable computing platforms enable rapid prototyping of arbitrary logic, but purely spatial fabrics suffer from issues with scalability and power consumption. Novel reconfigurable frameworks are being developed which similarly allow arbitrary function mapping, but do so with a mixture of spatial and temporal computing, improving scalability and energy efficiency over purely spatial fabrics. Embedded memories within these frameworks enable rapid function evaluation through lookup table operations, making the memory read/write behavior and power consumption critical design considerations. Emerging nonvolatile nanoscale memories demonstrate enhanced cell density, reliability, and read access performance over modern memory devices, promising vast improvements in energy efficiency for memory-based reconfigurable hardware platforms. Using Spintronic memory, an average 5% improvement in EDP over FPGA can be achieved in a memory-based framework, and tailoring the mapping to exploit features of spintronic memory can further improve EDP an average 1.6%.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129318499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Differential current-mode clock distribution 差分电流模式时钟分布
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282042
Riadul Islam, H. Fahmy, Ping-Yao Lin, Matthew R. Guthaus
{"title":"Differential current-mode clock distribution","authors":"Riadul Islam, H. Fahmy, Ping-Yao Lin, Matthew R. Guthaus","doi":"10.1109/MWSCAS.2015.7282042","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282042","url":null,"abstract":"In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK-Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential current-mode clock distribution, the differential technique saves 62% and 17% power compared to a conventional VM and a previous current-mode (CM) clock network, respectively.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Improving video-based resting heart rate estimation: A comparison of two methods 改进基于视频的静息心率估计:两种方法的比较
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282155
J. Choe, Dahjung Chung, A. Schwichtenberg, E. Delp
{"title":"Improving video-based resting heart rate estimation: A comparison of two methods","authors":"J. Choe, Dahjung Chung, A. Schwichtenberg, E. Delp","doi":"10.1109/MWSCAS.2015.7282155","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282155","url":null,"abstract":"Recent advancements in video processing make video-based heart rate (HR) estimation possible. Building on this burgeoning field, we adapted an existing video-based HR estimation method to produce more robust and accurate results. Specifically, we removed periodic signals from the recording environment by identifying (and removing) frequency clusters that are present the face region and background. This adaptive passband filter generates more accurate HR estimates and allows other applied filters to work more effectively.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134330096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Digitally programmable offset compensation of comparators in flash ADCs for hybrid ADC architectures 用于混合ADC架构的闪存ADC中比较器的数字可编程偏移补偿
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282059
Marina Zlochisti, Seyed Alireza Zahrai, M. Onabajo
{"title":"Digitally programmable offset compensation of comparators in flash ADCs for hybrid ADC architectures","authors":"Marina Zlochisti, Seyed Alireza Zahrai, M. Onabajo","doi":"10.1109/MWSCAS.2015.7282059","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282059","url":null,"abstract":"This paper presents an offset calibration approach that exploits the dynamic characteristics of a comparator to achieve a wide linear tuning range by placing varactors at two different internal nodes: the drains of the input pairs (Di nodes) for high linearity, and the output nodes for wider compensation range. The comparators are placed in a 3-bit 1GS/s flash ADC that will be integrated into an 8-bit hybrid ADC architecture. A digital calibration scheme controls the gate voltages of the varactors and detects the minimum offset condition. The proposed configuration was simulated with a transistor-level flash ADC design in 0.13μm CMOS technology and a Verilog-A behavioral implementation of the calibration circuitry. The ADC consumes 1.48mW of power (excluding the calibration circuitry, flip-flops and encoder) from a 1.2V voltage supply. Monte Carlo simulation results indicate that the method reduces the 3-sigma input offset of the comparator from 36.9mV to 1.6mV. The simulated effective number of bits (ENOB) of the flash ADC is 2.96 bits.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"805 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123289638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 8–14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology 基于16nm CMOS技术的8 - 14ghz无变容电流控制LC振荡器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282096
Somnath Kundu, V. Kireev, C. Kim
{"title":"A 8–14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology","authors":"Somnath Kundu, V. Kireev, C. Kim","doi":"10.1109/MWSCAS.2015.7282096","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282096","url":null,"abstract":"This paper presents a new concept of fine frequency tuning in a differential LC oscillator by injecting quadrature phase shifted current into the tank that can replace the use of a conventional varactor, eliminating all limitations associated with it, such as specific bias voltage requirement, limited Q-factor, technology/process uncertainties, model accuracy etc. Wide tuning range of 8-14 GHz is achieved by 5-bit switched capacitor array distributed across the exit legs of the inductor. The circuit is implemented in 16nm CMOS technology. Oscillator core consumes 2.85mW power from 0.9V supply at 10GHz frequency for 400mV single-ended swing. Phase noise is - 108dBc/Hz at 1MHz offset for no tuning current injection.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A robust cross-regulation-suppressed single-inductor multiple-output dc-dc converter with duty-regulated comparator control 具有稳压比较器控制的鲁棒交叉调节抑制单电感多输出dc-dc变换器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282117
Yanqi Zheng, M. Ho, K. Leung, Jianping Guo, Hua Chen
{"title":"A robust cross-regulation-suppressed single-inductor multiple-output dc-dc converter with duty-regulated comparator control","authors":"Yanqi Zheng, M. Ho, K. Leung, Jianping Guo, Hua Chen","doi":"10.1109/MWSCAS.2015.7282117","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282117","url":null,"abstract":"A robust cross-regulation-suppressed single-inductor multiple-output (SIMO) dc-dc converter with duty-regulated comparator control is proposed. The control scheme effectively combines comparator-based and linear-compensator-based controllers to achieve fast load-transient response and low cross regulation to other output channels simultaneously. The control algorithm does not rely on duty-inductor-current feed-forward which is sensitive to the accuracy of inductor-current sensor. As a result, it can provide robust cross-regulation suppression for a wide range of loading for the SIMO dc-dc converter. Moreover, together with the average-inductor-current control, the proposed control algorithm is suitable for SIMO dc-dc converter which has auto-buck-boost property for each sub-converter, which makes the SIMO converter suitable for dynamic voltage scaling applications.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122894848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-chip digital calibration for automatic input impedance boosting during biopotential measurements 在生物电位测量过程中用于自动输入阻抗提升的片上数字校准
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282021
Seyed Alireza Zahrai, Li Xu, Chun-hsiang Chang, Kainan Wang, Ibrahim Farah, M. Onabajo
{"title":"On-chip digital calibration for automatic input impedance boosting during biopotential measurements","authors":"Seyed Alireza Zahrai, Li Xu, Chun-hsiang Chang, Kainan Wang, Ibrahim Farah, M. Onabajo","doi":"10.1109/MWSCAS.2015.7282021","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282021","url":null,"abstract":"An On-chip digital calibration system is presented to adaptively improve the input impedance of analog front-ends in biopotential measurement systems. The calibration unit controls two 8-bit capacitor banks to generate a negative capacitance and to significantly increase the input impedance of an instrumentation amplifier to above 500MΩ. An oscillation detection scheme protects the system from instability. Simulation results endorse that the calibration scheme is reliable in the presence of process variations. The calibration logic unit was designed, laid out and simulated in 130nm CMOS technology with a 1.2V supply. It consumes 1.2 μW of power and 0.062 mm2 of chip area.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114167515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller 一个12位20毫秒/秒的SAR ADC，具有改进的内部时钟发生器和SAR控制器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282061
Xuan Li, Shuo Huang, Jianjun J. Zhou, Xiaoyong Li
{"title":"A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller","authors":"Xuan Li, Shuo Huang, Jianjun J. Zhou, Xiaoyong Li","doi":"10.1109/MWSCAS.2015.7282061","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282061","url":null,"abstract":"A 12-bit 20-MS/s charge redistribution successive approximation register analog-to-digital converter in a 65-nm CMOS technology is presented in this paper. To address the issue of long DAC settling time in bit-conversion, an improved internal clock generator is proposed. In addition, a novel SAR controller is introduced to minimize the critical path and improve the conversion speed. Simulation results show that the ADC achieves SNDR of 69.6 dB and SFDR of 79.9 dB with a 9.82-MHz sine-wave input while dissipating power consumption of 2.1 mW from a 1.2-V supply.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129459703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration 一个150 MHz带宽的连续时间ΔΣ调制器在28纳米CMOS与DAC校准
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282054
Rui Wang, Y. You, Guoying Wu, X. Wen, T. He, Jinghong Chen, K. Azadet, P. Gui
{"title":"A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration","authors":"Rui Wang, Y. You, Guoying Wu, X. Wen, T. He, Jinghong Chen, K. Azadet, P. Gui","doi":"10.1109/MWSCAS.2015.7282054","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282054","url":null,"abstract":"This paper presents transistor-level design of a 150 MHz bandwidth continuous-time (CT) ΔΣ modulator in a 0.85 V 28 nm CMOS process. Architectural-level design tradeoff for the high bandwidth requirement is discussed. A stand-alone DAC calibration scheme that suits the high-speed modulator is proposed for linearization. Simulation results show that the modulator achieves signal-to-noise-and-distortion ratio (SNDR) of 71 dB and spur-free dynamic range (SFDR) of 90 dB.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125859758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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