Energy-efficient reconfigurable computing using Spintronic memory

Abstract

Reconfigurable computing platforms enable rapid prototyping of arbitrary logic, but purely spatial fabrics suffer from issues with scalability and power consumption. Novel reconfigurable frameworks are being developed which similarly allow arbitrary function mapping, but do so with a mixture of spatial and temporal computing, improving scalability and energy efficiency over purely spatial fabrics. Embedded memories within these frameworks enable rapid function evaluation through lookup table operations, making the memory read/write behavior and power consumption critical design considerations. Emerging nonvolatile nanoscale memories demonstrate enhanced cell density, reliability, and read access performance over modern memory devices, promising vast improvements in energy efficiency for memory-based reconfigurable hardware platforms. Using Spintronic memory, an average 5% improvement in EDP over FPGA can be achieved in a memory-based framework, and tailoring the mapping to exploit features of spintronic memory can further improve EDP an average 1.6%.