差分电流模式时钟分布

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI:10.1109/MWSCAS.2015.7282042

Riadul Islam, H. Fahmy, Ping-Yao Lin, Matthew R. Guthaus

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引用次数: 7

摘要

在本文中，我们提出了一种差分电流模式脉冲触发器(DCMPFF)，用于低功耗时钟分布，采用具有代表性的45nm CMOS技术。实验结果表明，DCMPFF的时钟到输出(CLK-Q)延迟比传统的电压模式(VM)脉冲触发器快47%。当DCMPFF与差分电流模式时钟分布集成时，与传统VM和以前的CM时钟网络相比，差分技术分别节省62%和17%的功耗。

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Differential current-mode clock distribution

In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK-Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential current-mode clock distribution, the differential technique saves 62% and 17% power compared to a conventional VM and a previous current-mode (CM) clock network, respectively.

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2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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