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2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process 56 Gb/s PAM-4光接收机前端先进的FinFET工艺
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282209
Yu Kunzhi, Cheng Li, Tsung-Ching Huang, Ashkan Seyedi, Dacheng Zhou, Christopher Wilson, Dan Berkram, S. Palermo, Jonathan Q. Smela, Marco Fiorentino, R. Beausoleil
{"title":"56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process","authors":"Yu Kunzhi, Cheng Li, Tsung-Ching Huang, Ashkan Seyedi, Dacheng Zhou, Christopher Wilson, Dan Berkram, S. Palermo, Jonathan Q. Smela, Marco Fiorentino, R. Beausoleil","doi":"10.1109/MWSCAS.2015.7282209","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282209","url":null,"abstract":"This paper presents a 56Gb/s PAM-4 optical receiver analog frontend circuits which consists of three inverter stages TIA with resistive feedback in the first and third stages. An adaptively-tuned continuous-time linear equalizer (CTLE) is cascaded after the TIA for improved sensitivity and bandwidth. The overall gain is controlled by an automatic gain control (AGC) circuits to avoid the large input optical power saturates the TIA, thus distorting the PAM-4 signals. The frontend receiver circuits is designed in an advanced FinFET technology and overall gain achieves 68 dBO with a 22 GHz bandwidth. The simulated input referred current rms noise is 2.86 μA. Total chip power is 6.3 mW from a 0.83 V supply. The chip active area is 150μm × 100 μm.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126751610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A high-accuracy differential-capacitance-to-time converter for capacitive sensors 用于电容式传感器的高精度差分电容-时间转换器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282200
M. Nagai, S. Ogawa
{"title":"A high-accuracy differential-capacitance-to-time converter for capacitive sensors","authors":"M. Nagai, S. Ogawa","doi":"10.1109/MWSCAS.2015.7282200","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282200","url":null,"abstract":"A high-accuracy switched-capacitor (SC) differential-capacitance-to-time converter (DCTC) for capacitive sensors is presented for high-accuracy ratiometric operation. This circuit does not require component matching. Performances of the proposed circuit are simulated by HSPICE using 0.18 μm CMOS process parameters. Simulated results have demonstrated that 0.2% resolution is achievable. The op-amp and comparator were integrated using 0.18 μm triple-well CMOS process. Measured results using prototype circuits indicate that the gain and offset errors are 0.16% and 0.095% of the full scale, respectively. The proposed circuit is suited for co-integration with MEMS-type sensors and microcontroller-based measurement system.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131309801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A CMOS ripple detector for integrated voltage regulator testing 用于集成稳压器测试的CMOS纹波检测器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/DFT.2015.7315152
Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, M. Margala
{"title":"A CMOS ripple detector for integrated voltage regulator testing","authors":"Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, M. Margala","doi":"10.1109/DFT.2015.7315152","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315152","url":null,"abstract":"This paper will present an RMS based ripple sensor for testing of fully integrated voltage regulators. A DC signal which is proportional to the input ripple amplitude is generated. Final digital pass/fail signal is obtained with a clocked comparator. The sensor can detect a peak-to-peak ripple voltage of up to 50 millivolts on the 1.2 volts supply rail and has 220 MHz bandwidth. The sensor is designed using IBM 90 nm CMOS technology and its functionality is verified in Cadence Virtuoso simulation environment.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131474144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Adaptively-tunable RF photonic filters 自适应可调谐射频光子滤波器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282206
Shengchang Cai, Gihoon Choo, E. Z. Tabasy, Binhao Wang, K. Entesari, S. Palermo
{"title":"Adaptively-tunable RF photonic filters","authors":"Shengchang Cai, Gihoon Choo, E. Z. Tabasy, Binhao Wang, K. Entesari, S. Palermo","doi":"10.1109/MWSCAS.2015.7282206","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282206","url":null,"abstract":"The emergence of silicon photonics has enabled potential implementations of RF photonic filters with the size, weight, and power requirements of radio systems with small form factors. This paper presents a fourth-order elliptic digital filter designed in the optical domain with all-pass filter (APF) unit cells. A monitor-based adaptive tuning algorithm is proposed to calibrate the optical filter response with high accuracy and provide rapid filter reconfiguration.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131569254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 15.5-mW 20-GSps 4-bit charge-steering flash ADC 15.5 mw 20-GSps 4位电荷转向闪存ADC
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282153
Mostafa M. Ayesh, S. Ibrahim, M. Aboudina
{"title":"A 15.5-mW 20-GSps 4-bit charge-steering flash ADC","authors":"Mostafa M. Ayesh, S. Ibrahim, M. Aboudina","doi":"10.1109/MWSCAS.2015.7282153","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282153","url":null,"abstract":"This paper presents a 4-bit 20-GSps time-interleaved flash ADC for an ADC-based high-speed serial-link equalizer. The ADC is designed and simulated in a 65-nm CMOS technology. It dissipates 15.5 mW from a 1-V supply while operating at 20 GSps. Low power consumption is achieved by utilizing charge-steering concept, sharing single reference ladder across all the four interleaved branches, and merging the dynamic latch into the pre-amplifier of the comparator. Results show that for a sinusoidal input frequency of 9.84 GHz with an amplitude of 600 mVdiff, the SNDR of the digital output is 23.9 dB, SFDR is 33.6 dB, and the effective number of bits (ENOB) is 3.67 bits.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132488405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Single ion channel CMOS electrochemical instrument for high throughput recording arrays 用于高通量记录阵列的单离子通道CMOS电化学仪器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282111
Haitao Li, Sina Parsnejad, A. Mason
{"title":"Single ion channel CMOS electrochemical instrument for high throughput recording arrays","authors":"Haitao Li, Sina Parsnejad, A. Mason","doi":"10.1109/MWSCAS.2015.7282111","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282111","url":null,"abstract":"This paper presents instrumentations for high throughput single ion channel recording array used for proteomics. The instrumentations incorporates two-stage amplifier using shared operational transconductance amplifier structure. The proposed sensor frontend reduces power consumption and area of circuit without any performance degradations in terms of bandwidth and noise. Two compact, low noise, low power circuits are introduced to address the proposed amplifier structure. As a results, over 400 ion channels are implemented on a single chip. Design #1 is suitable for recording ion currents as low as 20pA within 9kHz bandwidth using minimal power. Design #2 is able to sense input currents as low as 10pA within a maximum bandwidth of 100kHz.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130905855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A reference-less multilevel memristor based RRAM module 基于RRAM模块的无参考多电平忆阻器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282147
Ahmed A. M. Emara, M. Ghoneima
{"title":"A reference-less multilevel memristor based RRAM module","authors":"Ahmed A. M. Emara, M. Ghoneima","doi":"10.1109/MWSCAS.2015.7282147","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282147","url":null,"abstract":"This paper presents a robust reference-less multilevel memristor based Resistive RAM (RRAM) module. In contrast to similar multilevel RRAMs, the proposed multilevel module eliminates the need for any comparing reference level. Because of the use of a differential 1T2M memory cell, data decoding is performed with traditional standard cells. On the other hand, no feedback loops are needed to ensure read, write and data decoding correctness. In addition, the proposed module is pinout compatible with the traditional 6T SRAM module. Simulation results, along with a comparison with other memristor based multilevel modules are presented.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130534169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp 在两级CMOS运算放大器中使用翻转电压跟随器进行电压缓冲补偿
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282199
S. Pakala, M. Manda, Punith R. Surkanti, A. Garimella, P. Furth
{"title":"Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp","authors":"S. Pakala, M. Manda, Punith R. Surkanti, A. Garimella, P. Furth","doi":"10.1109/MWSCAS.2015.7282199","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282199","url":null,"abstract":"In Miller and current buffer compensation techniques, the compensation capacitor often loads the output node. If a voltage buffer is used in feedback, the compensation capacitor obviates the loading on the output node. In this paper, we introduce an implementation of a voltage buffer compensation using a Flipped Voltage Follower (FVF) for stabilizing a two-stage CMOS op-amp. The op-amps are implemented in a 180-nm CMOS process with a power supply of 1.8V while operating with a quiescent current of 110μA. Results indicate that the proposed voltage buffer compensation using FVF improves the Unity Gain Frequency from 5.5MHz to 12.2MHz compared to Miller compensation. Also, the proposed technique enhances the transient response while lowering the compensation capacitance by 47% and 17.7% compared to Miller and common-drain compensation topologies. Utilization of FVF or its variants as a voltage buffer in a feedback compensation network has wide potential applications in the analog design space.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115255244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
High voltage measurements using slab coupled optical sensors (SCOS) 利用平板耦合光学传感器(SCOS)进行高压测量
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282175
L. Shumway, N. Stan, F. Seng, Rex King, R. Selfridge, S. Schultz
{"title":"High voltage measurements using slab coupled optical sensors (SCOS)","authors":"L. Shumway, N. Stan, F. Seng, Rex King, R. Selfridge, S. Schultz","doi":"10.1109/MWSCAS.2015.7282175","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282175","url":null,"abstract":"One of the most common methods used to measure high voltage is using a voltage divider. While this method is fairly reliable for most low frequency high voltage measurements, the voltage divider encounters difficulty when measuring higher frequency voltage signals. In these instances, the signal measured by the voltage divider becomes susceptible to distortion and inaccuracy. One solution to measuring voltages where a voltage divider would not suffice is using an electrode structure in conjunction with a fiber-based electric field sensor. A high voltage generator was constructed utilizing automotive ignition coils and was used in a capacitor-charging circuit. The voltage on the capacitor was measured using a common resistive voltage divider as well as with a fiber-based electric field sensor. Where a resistor divider was not reliable in characterizing the system, the optical sensor was successful in measuring the charge and discharge voltages of the capacitor circuit.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115753821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An asymmetric VHF self-oscillating DC-DC converter with integrated transformer 带集成变压器的非对称甚高频自振荡DC-DC变换器
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282018
R. Akbar, I. Filanovsky, Jani K. Jarvenhaara, N. Tchamov
{"title":"An asymmetric VHF self-oscillating DC-DC converter with integrated transformer","authors":"R. Akbar, I. Filanovsky, Jani K. Jarvenhaara, N. Tchamov","doi":"10.1109/MWSCAS.2015.7282018","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282018","url":null,"abstract":"The paper presents a self-oscillating DC-DC integrated converter which is operable in the frequency range of 200MHz-260MHz. The circuit includes a cascoded power stage, and an integrated transformer. The primary of the transformer provides the transmission of power to the converter load. The secondary provides the feedback signal to the gates of cascoded transistors in the power stage. The feedback circuit includes a duty cycle detector and a pulse-shaping circuit. A detailed analysis of duty cycle detector operation is given. The conditions for a smooth start-up are indicated as well. The circuit was designed and simulated for 45 nm CMOS technology, and the calculated parameters of the duty cycle detector are compared with that of the extracted from layout converter.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"62 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113943277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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