A simple ramp generator with level spreading for SEIR based ADC BIST circuit

Abstract

In ADC BIST testing circuit, ramp signal is the most widely used stimulus because of its simple structure and ease of control. In addition, with SEIR algorithm, the linearity requirement of the ramp signal is highly relaxed. But for high resolution ADC BIST testing, the ramp signal must be repetitive for acquiring valid data because a single ramp will cost large area, which is not acceptable for BIST solution. However, the repetitive ramp signals that is synchronized by on chip clock will cause collected data to be useless, because voltage levels sampled on every ramp are the same. For accomplishing different sampling voltages on each ramp signal, a method of introducing level spreading to every ramp signal is proposed in this paper. An 8-bit non-linear DAC as level-spreading generator is designed to provide the number of voltage levels required. The proposed control circuit for BIST consists of an 8-bit counter and end-detector without decoders. Simulation results show that the proposed method works well for linearity test based on SEIR algorithm, while the non-linearity of level spreading DAC barely impacts test results.