基于δ σ的有限脉冲响应滤波器在脑电信号处理中的应用

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI:10.1109/MWSCAS.2015.7282192

Yifei Liu, Wei Tang

{"title":"基于δ σ的有限脉冲响应滤波器在脑电信号处理中的应用","authors":"Yifei Liu, Wei Tang","doi":"10.1109/MWSCAS.2015.7282192","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a Finite Impulse Response Filter based on Delta Sigma Signal Processing. Both input and output of the proposed circuit are encoded as second-order Delta Sigma bit-streams. The design is realized using a Delta Sigma adder based on an input counter. The Delta Sigma adder can also be used as a coefficient multiplier. Using the proposed Delta Sigma adder and coefficient multiplier, an Finite Impulse Response filter is designed for Electroencephalogram signal processing. Simulation and synthesis results are shown based on IBM 180nm CMOS technology. The proposed design achieves a Θ(N) complexity with N inputs and can work with higher-order Delta Sigma bit-streams.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Delta Sigma based Finite Impulse Response Filter for EEG Signal Processing\",\"authors\":\"Yifei Liu, Wei Tang\",\"doi\":\"10.1109/MWSCAS.2015.7282192\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a Finite Impulse Response Filter based on Delta Sigma Signal Processing. Both input and output of the proposed circuit are encoded as second-order Delta Sigma bit-streams. The design is realized using a Delta Sigma adder based on an input counter. The Delta Sigma adder can also be used as a coefficient multiplier. Using the proposed Delta Sigma adder and coefficient multiplier, an Finite Impulse Response filter is designed for Electroencephalogram signal processing. Simulation and synthesis results are shown based on IBM 180nm CMOS technology. The proposed design achieves a Θ(N) complexity with N inputs and can work with higher-order Delta Sigma bit-streams.\",\"PeriodicalId\":216613,\"journal\":{\"name\":\"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2015.7282192\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2015.7282192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文提出了一种基于δ σ信号处理的有限脉冲响应滤波器的设计。所提出的电路的输入和输出都被编码为二阶Delta Sigma比特流。该设计采用基于输入计数器的δ σ加法器实现。加法器也可用作系数乘法器。利用所提出的δ σ加法器和系数乘法器，设计了一种用于脑电图信号处理的有限脉冲响应滤波器。给出了基于IBM 180nm CMOS技术的仿真和合成结果。提出的设计在N个输入时实现Θ(N)复杂度，并且可以处理高阶Delta Sigma比特流。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Delta Sigma based Finite Impulse Response Filter for EEG Signal Processing

This paper presents the design of a Finite Impulse Response Filter based on Delta Sigma Signal Processing. Both input and output of the proposed circuit are encoded as second-order Delta Sigma bit-streams. The design is realized using a Delta Sigma adder based on an input counter. The Delta Sigma adder can also be used as a coefficient multiplier. Using the proposed Delta Sigma adder and coefficient multiplier, an Finite Impulse Response filter is designed for Electroencephalogram signal processing. Simulation and synthesis results are shown based on IBM 180nm CMOS technology. The proposed design achieves a Θ(N) complexity with N inputs and can work with higher-order Delta Sigma bit-streams.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

自引率

0.00%

发文量