Current voltage characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET)

Abstract

This paper presents the current-voltage (I-V) characteristics of the recently proposed Silicon-on-Ferroelectric Insulator Field Effect Transistor (SOFFET). In this work we have concentrated on Partially Depleted (PD) structure. PD-SOFFET is based on the silicon-on-insulator (SOI) device technology and utilizes a negative capacitance that can be achieved by inserting a layer of ferroelectric insulator inside the bulk silicon substrate of the device. The negative capacitance (NC) effect can provide an internal signal boosting that leads to steeper subthreshold slope, which is the prime requirement for ultra-low-power circuit operation. Here we have analyzed the impacts of channel doping profile on the behavior of the proposed PD-SOFFET. The major focus of this paper is the investigation of the current-voltage (I-V) characteristics of the proposed device in both the subthreshold and the saturation regions.