Proceedings of the Fifth Asian Test Symposium (ATS'96)最新文献_第3页

Partially parallel scan chain for test length reduction by using retiming technique 采用重定时技术减少测试长度的部分并行扫描链

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555143

Y. Higami, S. Kajihara, K. Kinoshita

引用次数: 3

Formal verification of self-testing properties of combinational circuits 组合电路自检特性的形式化验证

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555147

K. Kawakubo, Koji Tanaka, H. Hiraishi

引用次数: 0

On-line testing in digital neural networks 数字神经网络在线测试

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555174

S. Demidenko, V. Piuri

引用次数: 5

A pragmatic, systematic and flexible synthesis for testability methodology 一个实用的，系统的和灵活的可测试性方法的综合

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555169

V. Alves, A. Antunes, M. Marzouki

引用次数: 0

AND/EXOR-based synthesis of testable KFDD-circuits with small depth 基于AND/ exoro的小深度可测试kfdd电路合成

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555152

H. Hengster, R. Drechsler, B. Becker, Stefan Eckrich, T. Pfeiffer

引用次数: 11

Easily testable data path allocation using input/output registers 易于测试的数据路径分配使用输入/输出寄存器

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555151

L. Huang, Jing-Yang Jou, S. Kuo, Wen-Bin Liao

引用次数: 2

Redundancy identification using transitive closure 使用传递闭包的冗余标识

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555127

V. Agrawal, M. Bushnell, Qing Lin

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引用次数: 15

BIST testability enhancement of system-level circuits: experience with an industrial design 系统级电路的BIST可测试性增强:具有工业设计经验

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555162

Kowen Lai, C. Papachristou

引用次数: 2

Constructing an edge-route guaranteed optimal fault-tolerant routing for biconnected graphs 构造双连通图的边路由保证最优容错路由

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555148

Yupin Luo, Shiyuan Yang, D. Hu

引用次数: 0

Hierarchical test generation with built-in fault diagnosis 内置故障诊断的分层测试生成

Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555130

D. Stroobandt, J. V. Campenhout

引用次数: 4