{"title":"Hybrid pin control using boundary-scan and its applications","authors":"W. Ke","doi":"10.1109/ATS.1996.555135","DOIUrl":"https://doi.org/10.1109/ATS.1996.555135","url":null,"abstract":"Boundary-Scan (B-S) has been widely used for interconnect testing. It allows all pins of a B-S chip to be controlled uniformly by either system or B-S logic. The requirement that all pins are controlled by the same logic limits B-S usage for many applications. We propose a new B-S instruction, called PINCONTROL, to allow mixed control of chip pins. That is, each pin can be individually configured to be controlled by the system or B-S logic. In this paper we shall demonstrate the application of this instruction for fault injection and inter-chip path delay testing.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127835817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Yield improvement by test error cancellation","authors":"Jwu E. Chen","doi":"10.1109/ATS.1996.555168","DOIUrl":"https://doi.org/10.1109/ATS.1996.555168","url":null,"abstract":"While an integrated circuit is fabricated and tested, errors may be introduced during manufacturing and testing processes. An IC development flow driven by yield improvement, which includes two stages of testing evaluations, called engineering and production runs, for test error classification and cancellation, is proposed in this paper. Six error-syndromes including mask, process, scrape, probe-card, probe-pin, and test-specification errors are classified by wafer map analysis. Test Errors can be canceled by either re-testing or re-adjusting the test-specification derived from designer/application-engineer and test engineer. An ASIC CMOS chip is used to validate the proposed testing process and the yield of this product is improved up to 16% in production line.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133987876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"E-groups: a new technique for fast backward propagation in system-level test generation","authors":"M. Nicolaidis, R. Parekhji, M. Boudjit","doi":"10.1109/ATS.1996.555133","DOIUrl":"https://doi.org/10.1109/ATS.1996.555133","url":null,"abstract":"This paper presents a new test pattern generation technique for complex systems. It focusses on test vector propagation through the individual blocks in the system. The technique is based on an easy identification of input-output pairs in each block. E (equality)-groups are formed for each block such that all the input vectors producing an identical output are grouped together. Such a grouping speeds up the task of backward propagation. In contrast to earlier methods, which considered the circuit structure for propagation, this method uses a functional approach and propagates the entire vector in one step. It is especially relevant to systems which consist of several blocks through which the test vector must be propagated. Results show that a significant reduction in the test generation time is possible.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114856297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Jarwala, P. W. Rutkowski, Shianling Wu, C. W. Yau
{"title":"Lessons learned from practical applications of BIST/B-S technology","authors":"N. Jarwala, P. W. Rutkowski, Shianling Wu, C. W. Yau","doi":"10.1109/ATS.1996.555167","DOIUrl":"https://doi.org/10.1109/ATS.1996.555167","url":null,"abstract":"Since Lucent Technologies (formerly AT&T) launched the Built-In Self-Test/Boundary-Scan (BIST/B-S) program in mid 1980's, over 200 devices and 80 circuit packs have incorporated BIST/B-S. These are from over 25 different project areas in various business units including Switching, Transmission, Wireless, Micro-Electronics, Federal Systems, and Consumer Products. Furthermore, since the early 1990's we have begun to see the full life-cycle impact of BIST and Boundary-Scan as a large quantity of hardware with BIST/B-S has gone full-cycle from design through manufacturing. We expect the steady growth in designs with BIST/B-S to continue and feel that the time is right to share our experiences and lessons learned from all levels: device, board, and system.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115708040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A practical implementation of dynamic testing of an AD converter","authors":"Y. Ting, L. Chao, W. Chao","doi":"10.1109/ATS.1996.555165","DOIUrl":"https://doi.org/10.1109/ATS.1996.555165","url":null,"abstract":"This paper presents a practical testing system which can measure the dynamic parameters such as effective bits (EB), signal to noise ratio (SNR), differential and integral nonlinearity (DNL and INL) of an AD converter. For practical implementation we propose a mixed frequency estimation algorithm with weighted least square method to estimate the EB. Furthermore we combine the spectral average method with frequency domain estimation to measure the SNR and use the histogram method to calculate the DNL and the INL. For practical purpose, we choose a logical analyzer as the high speed data acquisition device and a PC as the instrument controller. Two programmable signal generators with very low harmonic distortion are used for signal source of the ADC Testing. All the instruments are controlled by the PC through GPIB with a test software. Finally we apply the proposed test system and algorithm to measure the dynamic parameters of a real ADC (Datel ADC-HS12B). Results show that the proposed test system and methods are fast and accurate. Users can test the ADC automatically without worrying about the expensive testing instruments, interface problems and complex algorithms which may occur in other ADC testing systems.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114746055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On design of fail-safe cellular arrays","authors":"N. Kamiura, Y. Hata, K. Yamato","doi":"10.1109/ATS.1996.555145","DOIUrl":"https://doi.org/10.1109/ATS.1996.555145","url":null,"abstract":"In this paper, we discuss the design of a fail-safe cellular array composed of switch cells. First, we show the design method using a binary decision diagram. Next, we assume stuck-at-faults of switch cells to be fault models and discuss the fail-safe property for our array. For all the single faults and part of the multiple faults, our array keeps the fail-safe property. Next, for our arrays realizing randomly generated functions, we derive the ratio of the number of double faults that never break the fail-safe property to the total number of double faults. Finally, in order to demonstrate the advantages of our array, we compare our array with other arrays.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123889263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}