Yield improvement by test error cancellation

Abstract

While an integrated circuit is fabricated and tested, errors may be introduced during manufacturing and testing processes. An IC development flow driven by yield improvement, which includes two stages of testing evaluations, called engineering and production runs, for test error classification and cancellation, is proposed in this paper. Six error-syndromes including mask, process, scrape, probe-card, probe-pin, and test-specification errors are classified by wafer map analysis. Test Errors can be canceled by either re-testing or re-adjusting the test-specification derived from designer/application-engineer and test engineer. An ASIC CMOS chip is used to validate the proposed testing process and the yield of this product is improved up to 16% in production line.